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PDF LTC3863 Data sheet ( Hoja de datos )
| Número de pieza | LTC3863 | |
| Descripción | DC/DC Controller | |
| Fabricantes | Linear Technology | |
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LTC3863
60V Low IQ Inverting
DC/DC Controller
Features
n Wide Operating VIN Range: 3.5V to 60V
n Wide Negative VOUT Range: –0.4V to Beyond –150V
n Low Operating IQ = 70µA
n Strong High Voltage MOSFET Gate Driver
n Constant Frequency Current Mode Architecture
n Verified FMEA for Adjacent Pin Open/Short
n Selectable High Efficiency Burst Mode® Operation or
Pulse-Skipping Mode at Light Loads
n Programmable Fixed Frequency: 50kHz to 850kHz
n Phase-Lockable Frequency: 75kHz to 750kHz
n Accurate Current Limit
n Programmable Soft-Start or Voltage Tracking
n Internal Soft-Start Guarantees Smooth Start-Up
n Low Shutdown IQ = 7µA
n Available in Small 12-Lead Thermally Enhanced
MSOP and DFN Packages
Applications
n Industrial and Automotive Power Supplies
n Telecom Power Supplies
n Distributed Power Systems
Description
The LTC®3863 is a robust, inverting DC/DC PMOS control-
ler optimized for automotive and industrial applications. It
drives a P-channel power MOSFET to generate a negative
output and requires just a single inductor to complete the
circuit. Output voltages from –0.4V to –150V are typically
achievable with higher voltages possible, only limited by
external components.
The LTC3863 offers excellent light load efficiency, draw-
ing only 70μA quiescent current in a user programmable
Burst Mode operation. Its peak current mode, constant
frequency PWM architecture provides for good control of
switching frequency and output current limit. The switch-
ing frequency can be programmed from 50kHz to 850kHz
with an external resistor and can be synchronized to an
external clock from 75kHz to 750kHz.
The LTC3863 offers programmable soft-start or output
tracking. Safety features include overvoltage, overcurrent
and short-circuit protection including frequency foldback.
The LTC3863 is available in thermally enhanced 12-lead
MSOP and 3mm × 4mm DFN packages.
L, LT, LTC, LTM, OPTI-LOOP, Linear Technology, Burst Mode and the Linear logo are registered
trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5731694.
Typical Application
4.5V to 16V Input, –5V/1.7A Output, 350kHz Inverting Converter
350kHz
27nF 14.7k
61.9k
0.47µF
RUN CAP
VIN
PLLIN/MODE
SS SENSE
GATE
ITH LTC3863
FREQ
SGND
PGND
VFBN
VFB
10µF +
25V
×2
16mΩ
VIN
100µF 4.5V TO 16V
20V
Si7129
10µHB540C 511k
33µF
×2
68pF
80.6k
3863 TA01a
VOUT
150µF
16V
–5V
1.7A
×2
Efficiency
90 VIN = 12V
80 VOUT = –5V
9
8
70
60 EFFICIENCY
7
6
50 5
40 PULSE-SKIPPING MODE 4
30 Burst Mode OPERATION 3
20 2
10
POWER LOSS
1
0
0.002
0.02 0.2
LOAD CURRENT (A)
0
2
3863 TA01b
For more information www.linear.com/3863
3863fa
1
1 page  
LTC3863
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
Pulse-Skipping Mode Operation
Waveforms
Burst Mode Operation
Waveforms
VOUT
50mV/DIV
VOUT
50mV/DIV
VSW
10V/DIV
IL
500mA/DIV
VIN = 12V
2µs/DIV
VOUT = –5V
ILOAD = 100mA
FIGURE 7 CIRCUIT
VSW
10V/DIV
IL
500mA/DIV
3863 G01
VIN = 12V
20µs/DIV
VOUT = –5V
ILOAD = 100mA
FIGURE 7 CIRCUIT
Transient Response:
Burst Mode Operation
ILOAD
1A/DIV
VOUT
200mV/DIV
IL
1A/DIV
3863 G02
VIN = 12V
VOUT = –5V
100µs/DIV
TRANSIENT = 100mA TO 1.6A
FIGURE 7 CIRCUIT
3863 G03
Transient Response:
Pulse-Skipping Mode Operation
Transient Response: Rising Edge
Pulse-Skipping Mode Operation
Transient Response: Falling Edge
Pulse-Skipping Mode Operation
ILOAD
1A/DIV
ILOAD
1A/DIV
ILOAD
1A/DIV
VOUT
200mV/DIV
IL
1A/DIV
VOUT
200mV/DIV
IL
1A/DIV
VOUT
200mV/DIV
IL
1A/DIV
VIN = 12V
100µs/DIV
VOUT = –5V
TRANSIENT = 100mA TO 1.6A
FIGURE 7 CIRCUIT
3863 G04
VIN = 12V
10µs/DIV
VOUT = –5V
TRANSIENT = 100mA TO 1.6A
FIGURE 7 CIRCUIT
3863 G05
VIN = 12V
10µs/DIV
VOUT = –5V
TRANSIENT = 1.6A TO 100mA
FIGURE 7 CIRCUIT
3863 G06
Normal Soft-Start
VIN
5V/DIV
VOUT1
2V/DIV
VOUT2
2V/DIV
TRACK/SS
200mV/DIV
VIN = 12V
1ms/DIV
VOUT1 = 5V
VOUT2 = –5V
ILOAD1 = ILOAD2 = 100mA
FIGURE 11 CIRCUIT
Soft-Start into a Prebiased Output
RUN
5V/DIV
VOUT1
2V/DIV
3863 G07
VOUT2
2V/DIV
TRACK/SS
200mV/DIV
VIN = 12V
1ms/DIV
VOUT1 = 5V, VOUT2 = –5V
PRE-BIAS1 = 2V, PRE-BIAS2 = –2V
ILOAD = 50mA
FIGURE 11 CIRCUIT
3863 G08
Output Tracking
VOUT2
2V/DIV
TRACK/SS
200mV/DIV
VOUT1
2V/DIV
VIN = 12V
20ms/DIV
VOUT1 = 5V
VOUT2 = –5V
ILOAD1 = ILOAD2 = 100mA
FIGURE 11 CIRCUIT
3863 G09
For more information www.linear.com/3863
3863fa
5
5 Page 
Operation
The start-up of the output voltage VOUT is controlled by
the voltage on the SS pin. When the voltage on the SS
pin is less than the 0.8V internal reference, the VFB pin is
regulated to the voltage on the SS pin. This allows the SS
pin to be used to program a soft-start by connecting an
external capacitor from the SS pin to signal ground. An
internal 10µA pull-up current charges this capacitor, creat-
ing a voltage ramp on the SS pin. As the SS voltage rises
from 0V to 0.8V, the output voltage VOUT rises smoothly
from zero to its final value.
Alternatively, the SS pin can be used to cause the start-up of
VOUT to track that of another supply. Typically, this requires
connecting the SS pin to an external resistor divider from
the other supply to ground (see Applications Information).
Under shutdown or UVLO, the SS pin is pulled to ground
and prevented from ramping up.
If the slew rate of the SS pin is greater than 1.2V/ms, the
output will track an internal soft-start ramp instead of the
SS pin. The internal soft-start will guarantee a smooth
start-up of the output under all conditions, including in the
case of a short-circuit recovery where the output voltage
will recover from near ground.
Light Load Current Operation (Burst Mode Operation
or Pulse-Skipping Mode)
The LTC3863 can be enabled to enter high efficiency Burst
Mode operation or pulse-skipping mode at light loads. To
select pulse-skipping operation, tie the PLLIN/MODE pin
to signal ground. To select Burst Mode operation, float
the PLLIN/MODE pin.
In Burst Mode operation, if the VFB is higher than the refer-
ence voltage, the error amplifier will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high, enabling sleep mode.
The ITH pin is then disconnected from the output of the
error amplifier and held at 0.55V.
LTC3863
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current to 70µA while the
load current is supplied by the output capacitor. As the
output voltage and hence the feedback voltage decreases,
the error amplifier’s output will rise. When the output
voltage drops enough, the ITH pin is reconnected to the
output of the error amplifier, the sleep signal goes low,
and the controller resumes normal operation by turning
on the external P-channel MOSFET on the next cycle of
the internal oscillator. In Burst Mode operation, the peak
inductor current has to reach at least 25% of current limit
for the current comparator, ICMP, to trip and turn the
P-channel MOSFET back off, even though the ITH voltage
may indicate a lower current setpoint value.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3863 will skip pulses during light loads. In
this mode, ICMP may remain tripped for several cycles and
force the external MOSFET to stay off, thereby skipping
pulses. This mode offers the benefits of smaller output
ripple, lower audible noise, and reduced RF interference,
at the expense of lower efficiency when compared to Burst
Mode operation.
Frequency Selection and Clock Synchronization
The switching frequency of the LTC3863 can be selected
using the FREQ pin. If the PLLIN/MODE pin is not being
driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through an
external resistor. Tying FREQ pin to signal ground selects
350kHz, while floating selects 535kHz. Placing a resistor
between FREQ pin and signal ground allows the frequency
to be programmed between 50kHz and 850kHz.
The phase-locked loop (PLL) on the LTC3863 will syn-
chronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
the turn-on edge of the external P-channel MOSFET to be
aligned with the rising edge of the synchronizing signal.
For more information www.linear.com/3863
3863fa
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3863.PDF ] | |
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