PDF SI53159 Data sheet ( Hoja de datos )

Número de pieza	SI53159
Descripción	FANOUT BUFFER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si53159 PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 NINE OUTPUT FANOUT BUFFER Features  PCI-Express Gen 1, Gen 2,  Up to nine buffered clocks Gen 3, and Gen 4 common clock  100 to 210 MHz clock input range    compliant  Supports Serial-ATA (SATA) at 100 MHz  Low power push-pull differential output buffers  No termination resistors required I2C support with readback capabilities Supports spread spectrum input Extended temperature: –40 to 85 oC  Output enable pins for all  3.3 V power supply buffered clocks  48-pin QFN package Applications  Network attached storage  Multi-function printers  Wireless access point  Servers Description The Si53159 is a high-performance, low additive jitter, PCIe clock buffer that can fan out nine PCIe clocks. The clock outputs are compliant to PCIe Gen 1, Gen 2, Gen 3, and Gen 4 specifications. The device has six hardware output enable control pins for enabling and disabling differential outputs. The small footprint and low power consumption makes the Si53159 the ideal clock solution for consumer and embedded applications. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie- learningcenter. Functional Block Diagram Ordering Information: See page 18. Pin Assignments 48 47 46 45 44 43 42 41 40 39 38 37 VDD_DIFF 1 36 DIFF8 VDD_DIFF 2 35 DIFF8 OE_DIFF01 3 34 VDD_DIFF OE_DIFF11 4 VDD_DIFF 5 VSS_DIFF 6 VSS_DIFF 7 OE_DIFF21 8 OE_DIFF31 9 OE_DIFF[4:5]1 10 OE_DIFF[6:8]1 11 VDD_DIFF 12 49 GND 33 DIFF7 32 DIFF7 31 DIFF6 30 DIFF6 29 VSS_DIFF 28 DIFF5 27 DIFF5 26 DIFF4 25 DIFF4 13 14 15 16 17 18 19 20 21 22 23 24 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Patents pending DIFFIN DIFFIN SCLK SDATA OE [8:0] Control & Memory Control RAM DIFF0 DIFF1 DIFF2 DIFF3 DIFF4 DIFF5 DIFF6 DIFF7 DIFF8 Rev. 1.1 12/15 Copyright © 2015 by Silicon Laboratories Si53159 1 page Si53159 Table 2. AC Electrical Specifications Parameter Symbol Condition Min DIFFIN at 0.7 V DIFFIN and DIFFIN Rising/Falling Slew Rate TR / TF Single ended measurement: VOL = 0.175 to VOH = 0.525 V (Averaged) 0.6 Differential Input High Voltage Differential Input Low Voltage Crossing Point Voltage at 0.7 V Swing VIH 150 VIL — VOX Single-ended measurement 250 Vcross Variation Over All edges Differential Ringback Voltage Time before Ringback Allowed Absolute Maximum Input Voltage Absolute Minimum Input Voltage DIFFIN and DIFFIN Duty Cycle Rise/Fall Matching DIFF at 0.7 V VOX VRB TSTABLE VMAX VMIN TDC TRFM Single-ended measurement Measured at crossing point VOX Determined as a fraction of 2 x (TR – TF)/(TR + TF) — –100 500 –0.3 45 — Duty Cycle Clock Skew PCIe Gen1 Pk-Pk Jitter TDC TSKEW Pk-Pk Measured at 0 V differential Measured at 0 V differential PCIe Gen 1 45 — 0 PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 1.5 MHz < F < Nyquist 0 0 PCIe Gen 3 Phase Jitter RMSGEN3 Includes PLL BW 2–4 MHz, CDR = 10 MHz 0 Additive PCIe Gen 4 Phase Jitter RMSGEN4 Additive Cycle to Cycle Jitter TCCJ PCIe Gen 4 In buffer mode. Measured at 0 V differential — — Long-term Accuracy Rising/Falling Slew rate LACC TR / TF Measured at 0 V differential Measured differentially from ±150 mV — 2.5 Crossing Point Voltage at 0.7 V Swing VOX 300 Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Typ — — — — — — — — — — — — — — — — — — 20 — — — Max Unit 4 V/ns — –150 550 mV mV mV 140 mV 100 mV — ps 1.15 V —V 55 % 20 % 55 % 50 ps 10 ps 0.5 ps 0.5 ps 0.10 ps 0.10 ps 50 ps 100 ppm 8 V/ns 550 mV Rev. 1.1 5 5 Page Si53159 Bit 1 8:2 9 10 18:11 19 27:20 28 29 Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Description Start Byte Read Protocol Bit Description 1 Start Slave address–7 bits 8:2 Slave address–7 bits Write 9 Write Acknowledge from slave 10 Acknowledge from slave Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start Acknowledge from slave 27:21 Slave address–7 bits Stop 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Rev. 1.1 11 11 Page

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