PDF SI53156 Data sheet ( Hoja de datos )

Número de pieza	SI53156
Descripción	FANOUT BUFFER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si53156 PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER Features  PCI-Express Gen 1, Gen 2, Gen 3,  Six PCI-Express buffered clock and Gen 4 common clock compliant outputs  Supports Serial ATA (SATA) at  Clock input spread tolerable 100 MHz  Supports LVDS outputs  100–210 MHz operation  I2C support with readback  Low power, push pull, differential capabilities output buffers  Extended temperature:   Internal termination for maximum integration  Dedicated output output enable pin for each  –40 to 85 oC 3.3 V power supply 32-pin QFN package Applications  Network attached storage  Multi-function printers  Wireless access point  Routers Description The Si53156 is a spread spectrum tolerant PCIe clock buffer that can source six PCIe clocks simultaneously. The device has six hardware output enable control inputs for enabling the respective differential outputs on the fly. The device also features output enable control through I2C communication. I2C programmability is also available to dynamically control skew, edge rate and amplitude on the true, compliment, or both differential signals on the clock outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Functional Block Diagram Ordering Information: See page 17. Pin Assignments 32 31 30 29 28 27 26 25 VDD 1 24 VDD OE2* 2 VDD 3 OE3* 4 OE4* 5 33 GND 23 DIFF5 22 DIFF5 21 VDD 20 DIFF4 OE5* 6 19 DIFF4 NC 7 18 DIFF3 VDD 8 17 DIFF3 9 10 11 12 13 14 15 16 *Note: Internal 100 kohm pull-up. DIFFIN DIFFIN SCLK SDATA OE [5:0] Control & Memory Control RAM DIFF0 DIFF1 DIFF2 DIFF3 DIFF4 DIFF5 Patents pending Rev. 1.1 12/15 Copyright © 2015 by Silicon Laboratories Si53156 1 page Si53156 Table 2. AC Electrical Specifications Parameter Symbol Condition Min DIFFIN at 0.7 V Input Frequency Range Rising and Falling Slew Rates for Each Clock Output Signal in a Given Differential Pair fin TR/TF Single ended measurement: VOL = 0.175 to VOH = 0.525 V (Averaged) 100 0.6 Differential Input High Voltage Differential Input Low Voltage Crossing Point Voltage at 0.7 V Swing VIH 150 VIL — VOX Single-ended measurement 250 Vcross Variation over all edges Differential Ringback Voltage Time before ringback allowed Absolute maximum input voltage Absolute minimum input voltage Duty Cycle for Each Clock Output Signal in a Given Differential Pair VOX VRB TSTABLE VMAX VMIN TDC Single-ended measurement — –100 500 — –0.3 Measured at crossing point VOX 45 Rise/Fall Matching DIFF at 0.7 V TRFM Determined as a fraction of 2 x (TR – TF)/(TR + TF) — Duty Cycle Clock Skew Additive Peak Jitter TDC TSKEW Pk-Pk Measured at 0 V differential Measured at 0 V differential 45 — 0 Additive PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 1.5 MHz< F < Nyquist Rate 0 0 Additive PCIe Gen 3 Phase Jitter RMSGEN3 Includes PLL BW 2–4 MHz (CDR = 10 MHz) 0 Additive PCIe Gen 4 Phase Jitter Additive Cycle to Cycle Jitter Long-term Accuracy Rising/Falling Slew rate RMSGEN4 TCCJ LACC TR / TF PCIe Gen 4 Measured at 0 V differential Measured at 0 V differential Measured differentially from ±150 mV — — — 2.5 Crossing Point Voltage at 0.7 V Swing VOX 300 Notes: 1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Typ — — — — — — — — — — — — — — — — — — — — — — — Max Unit 210 MHz 4 V/ns — –150 550 mV mV mV 140 mV 100 mV — ps 1.15 V —V 55 % 20 % 55 % 50 ps 10 ps 0.5 ps 0.5 ps 0.10 ps 0.10 ps 50 ps 100 ppm 8 V/ns 550 mV Rev. 1.1 5 5 Page Si53156 Bit 1 8:2 9 10 18:11 19 27:20 28 29 Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Description Start Byte Read Protocol Bit Description 1 Start Slave address–7 bits 8:2 Slave address–7 bits Write 9 Write Acknowledge from slave 10 Acknowledge from slave Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start Acknowledge from slave 27:21 Slave address–7 bits Stop 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Rev. 1.1 11 11 Page

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