PDF SI53154 Data sheet ( Hoja de datos )

Número de pieza	SI53154
Descripción	FANOUT BUFFER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si53154 PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 QUAD FANOUT BUFFER Features  PCI-Express Gen 1, Gen 2, Gen 3,  Four PCI-Express buffered clock and Gen 4 common clock outputs compliant  Clock input spread tolerable  Supports Serial ATA (SATA) at  Supports LVDS outputs 100 MHz  I2C support with readback  100–210 MHz operation capabilities  Low power, push pull, differential  Extended temperature:  output buffers Internal termination for maximum integration  –40 to 85 oC 3.3 V power supply  Dedicated output enable pin for  24-pin QFN package each output Applications  Network attached storage  Multi-function printers  Wireless access point  Routers Description The Si53154 is a spread spectrum tolerant PCIe clock buffer that can source four PCIe clocks simultaneously. The device has four hardware output enable control inputs for enabling the respective differential outputs on the fly. The device also features output enable control through I2C communication. I2C programmability is also available to dynamically control skew, edge rate and amplitude on the true, compliment, or both differential signals on the clock outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Functional Block Diagram Ordering Information: See page 17. Pin Assignments VDD 1 OE1* 2 VDD 3 VSS 4 OE2* 5 VDD 6 24 23 22 21 20 19 18 OE3* 17 VDD 25 GND 16 DIFF3 15 DIFF3 14 DIFF2 13 DIFF2 7 8 9 10 11 12 *Note: Internal 100 kohm pull-up. Patents pending DIFFIN DIFFIN SCLK SDATA OE [3:0] Control & Memory Control RAM DIFF0 DIFF1 DIFF2 DIFF3 Rev. 1.1 12/15 Copyright © 2015 by Silicon Laboratories Si53154 1 page Si53154 Table 2. AC Electrical Specifications Parameter DIFFIN at 0.7 V Symbol Condition Min Typ Max Unit Input Frequency Range fin 100 — 210 MHz Rising and Falling Slew Rates for Each Clock Output Signal in a Given Differential Pair TR / TF Single ended measurement: VOL = 0.175 to VOH = 0.525 V (Averaged) 0.6 — 4 V/ns Differential Input High Voltage VIH 150 — — mV Differential Input Low Voltage VIL — — –150 mV Crossing Point Voltage at VOX Single-ended measurement 250 — 550 mV 0.7 V Swing Vcross Variation over all Edges VOX Single-ended measurement — — 140 mV Differential Ringback Voltage VRB –100 — 100 mV Time before Ringback Allowed TSTABLE 500 — — ps Absolute Maximum Input Voltage VMAX — — 1.15 V Absolute Minimum Input Voltage VMIN –0.3 — —V Duty Cycle for Each Clock TDC Measured at crossing point VOX 45 — 55 % Output Signal in a Given Differential Pair Rise/Fall Matching TRFM Determined as a fraction of 2 x (TR – TF)/(TR + TF) — — 20 % DIFF at 0.7 V Duty Cycle Clock Skew Additive Peak Jitter TDC TSKEW Pk-Pk Measured at 0 V differential Measured at 0 V differential 45 — 55 % — — 50 ps 0 — 10 ps Additive PCIe Gen 2 Phase RMSGEN2 Jitter 10 kHz < F < 1.5 MHz 1.5 MHz< F < Nyquist Rate 0 — 0.5 ps 0 — 0.5 ps Additive PCIe Gen 3 Phase RMSGEN3 Jitter Includes PLL BW 2–4 MHz (CDR = 10 MHz) 0 — 0.10 ps Notes: 1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Rev. 1.1 5 5 Page Si53154 Bit 1 8:2 9 10 18:11 19 27:20 28 29 Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Data byte–8 bits Acknowledge from slave Stop Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Byte Read Protocol Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave Repeated start Slave address–7 bits Read Acknowledge from slave Data from slave–8 bits NOT Acknowledge Stop Rev. 1.1 11 11 Page

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