PDF SI53152 Data sheet ( Hoja de datos )

Número de pieza	SI53152
Descripción	FANOUT BUFFER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si53152 PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER Features  PCI-Express Gen 1, Gen 2, Gen 3,  Dedicated output enable pin for and Gen 4 common clock each clock compliant  Two PCI-Express buffered clock  Supports Serial ATA (SATA) at outputs 100 MHz  Supports LVDS outputs  100–210 MHz operation  I2C support with readback  Low power, push pull, differential capabilities output buffers  Extended temperature:  Internal termination for maximum –40 to 85 oC integration  3.3 V Power supply  24-pin QFN package Applications Ordering Information: See page 17  Network attached storage  Multi-function Printer  Wireless access point  Routers Pin Assignments Description The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source two PCIe clocks simultaneously. The device has two hardware output enable inputs for enabling the respective differential outputs on the fly. The device also features output enable control through I2C communication. I2C programmability is also available to dynamically control skew, edge rate and amplitude on the true, compliment, or both differential signals on the clock outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. VDD 1 NC 2 VDD 3 VSS 4 OE_DIFF0* 5 VDD 6 24 23 22 21 20 19 18 OE_DIFF1* 17 VDD 25 GND 16 DIFF1 15 DIFF1 14 DIFF0 13 DIFF0 7 8 9 10 11 12 *Note: Internal 100 kohm pull-up. Patents pending Functional Block Diagram DIFFIN DIFFIN SCLK SDATA OE [1:0] Control & Memory Control RAM DIFF0 DIFF1 Rev. 1.1 12/15 Copyright © 2015 by Silicon Laboratories Si53152 1 page Si53152 Table 2. AC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit DIFFIN at 0.7 V Input Frequency Range fin 100 — 210 MHz Rising and Falling Slew Rates for Each Clock Output Signal in a Given Differential Pair TR / TF Single ended measurement: VOL = 0.175 to VOH = 0.525 V (Averaged) 0.6 — 4 V/ns Differential Input High Voltage Differential Input Low Voltage Crossing Point Voltage at 0.7 V Swing VIH VIL VOX Single-ended measurement 150 — — mV — — –150 mV 250 — 550 mV Vcross Variation over all edges Differential Ringback Voltage Time before ringback allowed Absolute Maximum Input Voltage VOX VRB TSTABLE VMAX Single-ended measurement — –100 500 — — — — 140 mV 100 mV — ps 1.15 V Absolute Minimum Input Voltage VMIN –0.3 — —V Duty Cycle for Each Clock Output Signal in a Given Differential Pair Rise/Fall Matching DIFF at 0.7 V TDC Measured at crossing point VOX 45 — 55 % TRFM Determined as a fraction of 2 x (TR – TF)/(TR + TF) — — 20 % Duty Cycle Clock Skew Additive Peak Jitter TDC TSKEW Pk-Pk Measured at 0 V differential Measured at 0 V differential 45 — 55 % — — 50 ps 0 — 10 ps Additive PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 1.5 MHz< F < Nyquist Rate 0 — 0.5 ps 0 — 0.5 ps Additive PCIe Gen 3 Phase Jitter RMSGEN3 Includes PLL BW 2–4 MHz (CDR = 10 MHz) 0 — 0.10 ps Additive PCIe Gen 4 Phase Jitter RMSGEN4 PCIe Gen 4 — Additive Cycle to Cycle Jitter TCCJ Measured at 0 V differential — Long Term Accuracy LACC Measured at 0 V differential — Notes: 1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. — 0.10 ps — 50 ps — 100 ppm Rev. 1.1 5 5 Page Si53152 Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description 1 Start Byte Read Protocol Bit Description 1 Start 8:2 Slave address–7 bits 8:2 Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code–8 bits 18:11 Command Code–8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 27:21 Slave address–7 bits 29 Stop 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Rev. 1.1 11 11 Page

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