|
|
PDF SI5347 Data sheet ( Hoja de datos )
| Número de pieza | SI5347 | |
| Descripción | ANY-OUTPUT JITTER ATTENUATORS | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SI5347 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Si5347/46
D UAL/ Q UAD D S P L L A NY- F REQUENCY, A NY- O UTPUT J ITTER A TTENUATORS
Features
Four or two independent DSPLLs in a Automatic free-run and holdover modes
single monolithic IC
Fastlock feature for low nominal
Each DSPLL generates any output
bandwidths
frequency from any input frequency
Input frequency range:
Glitchless on-the-fly DSPLL frequency
changes
Differential: 8 kHz to 750 MHz
DCO mode: as low as 0.01 ppb steps
LVCMOS: 8 kHz to 250 MHz
Output frequency range:
per DSPLL
Core voltage:
Differential: up to 712.5 MHz
VDD: 1.8 V ±5%
LVCMOS: up to 250 MHz
Ultra low jitter:
VDDA: 3.3 V ±5%
Independent output clock supply pins:
<100 fs typ (12 kHz–20 MHz)
3.3, 2.5, or 1.8 V
Flexible crosspoints route any input to Output-output skew:
any output clock
<20 ps (typ) per DSPLL
Programmable jitter attenuation
bandwidth per DSPLL: 0.1 Hz to 4 kHz
programming range
Highly configurable outputs compatible
with LVDS, LVPECL, LVCMOS, CML,
Serial interface: I2C or SPI
In-circuit programmable with non-volatile
OTP memory
ClockBuilderTM Pro software tool
and HCSL with programmable signal
simplifies device configuration
amplitude
Si5347: Quad DSPLL, 4 input,
Status monitoring (LOS, OOF, LOL)
4 or 8 output, 64 QFN
Hitless input clock switching: automatic Si5346: Dual DSPLL, 4 input,
or manual
Locks to gapped clock inputs
4 output, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Device Selector Guide
Grade
Si5347A
Si5347C
Si5346A
Si5347B
Si5347D
Si5346B
PLLs/OUTs
4/8
4/4
2/4
4/8
4/4
2/4
Max Output Freq
712.5 MHz
712.5 MHz
712.5 MHz
350 MHz
350 MHz
350 MHz
Frequency Synthesis Modes
Integer + Fractional
Integer + Fractional
Integer + Fractional
Integer + Fractional
Integer + Fractional
Integer + Fractional
Applications
9x9 mm
7x7 mm
Ordering Information:
See section 8
Functional Block Diagram
XTAL/
REFCLK
Si5347 XA
XB
OSC
IN0 ÷FRAC
IN1 ÷FRAC
IN2 ÷FRAC
IN3 ÷FRAC
NVM
I2C/SPI
Control/
Status
DSPLL
A
DSPLL
B
DSPLL
C
DSPLL
D
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OTN Muxponders and Transponders
10/40/100G network line cards
GbE/10 GbE/100 GbE Synchronous
Ethernet (ITU-T G.8262)
Carrier Ethernet switches
Broadcast video
Description
The Si5347 is a high performance jitter attenuating clock multiplier which integrates four
any-frequency DSPLLs for applications that require maximum integration and independent
timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each DSPLL has
access to any of the four inputs and can provide low jitter clocks on any of the device
outputs. Based on 4th generation DSPLL technology, these devices provide any-frequency
conversion with typical jitter performance under 100 fs. Each DSPLL supports independent
free-run, holdover modes of operation, as well as automatic and hitless input clock
switching. The Si5347/46 is programmable via a serial interface with in-circuit
programmable non-volatile memory so that it always powers up in a known configuration.
Programming the Si5347/46 is easy with Silicon Labs’ ClockBuilder Pro software. Factory
pre-programmed devices are also available.
S i5 3 4 6
XTAL/
REFCLK
XA XB
OSC
IN0 ÷FRAC
÷ IN T
DSPLL
÷ IN T
IN1 ÷FRAC
A
÷ IN T
DSPLL
IN2 ÷FRAC
B ÷INT
IN3 ÷FRAC
NVM
I2C /SPI
C ontrol/
Status
OUT0
OUT1
OUT2
OUT3
Rev. 1.1 9/15
Copyright © 2015 by Silicon Laboratories
Si5347/46
1 page  
Si5347/46
Table 2. DC Characteristics (Continued)
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Output Buffer Supply Current
Total Power Dissipation
Symbol
IDDO
Pd
Test Condition
LVPECL Output3
@ 156.25 MHz
LVDS Output3
@ 156.25 MHz
3.3V LVCMOS4 output
@ 156.25 MHz
2.5V LVCMOS4 output
@ 156.25 MHz
1.8V LVCMOS4 output
@ 156.25 MHz
Si5347 Note 1,5
Si5346 Note 2,5
Min
—
—
—
—
—
—
—
Typ Max Unit
21 25 mA
15 18 mA
21 25 mA
16 18 mA
12 13 mA
980 1160 mW
840 1000 mW
Notes:
1. Si5347 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2. Si5346 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3. Differential outputs terminated into an AC coupled 100 load.
4. LVCMOS outputs measured into a 5-inch 50 PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5347/46 Family Reference Manual for
more details on register settings.
5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Differential Output Test Configuration
IDDO
OUT
OUT
50
0.1 µF
IDDO
100 OUT
50
0.1 µF
OUT
LVCMOS Output Test Configuration
Trace length 5
inches
50
499
0.1 µF
4.7 pF
56
50 Scope Input
499
0.1 µF
50 50 Scope Input
4.7 pF
56
Rev. 1.1
5
5 Page 
Si5347/46
Table 6. LVCMOS Clock Output Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Output Frequency
fOUT
0.0001 — 250 MHz
Duty Cycle DC fOUT <100 MHz 47 — 53 %
100 MHz < fOUT < 250 MHz
44 — 55
Output-to-Output Skew
Output Voltage High1, 2, 3
TSK
VOH
LVCMOS outputs
VDDO = 3.3 V
—
— 100 ps
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
IOH = –10 mA
IOH = –12 mA
VDDO x
0.75
—
—
—
—
V
OUTx_CMOS_DRV=3
IOH = –17 mA
——
VDDO = 2.5 V
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
IOH = –6 mA
IOH = –8 mA
VDDO x
0.75
—
—
—
—
V
OUTx_CMOS_DRV=3
IOH = –11 mA
——
VDDO = 1.8 V
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOH = –4 mA
IOH = –5 mA
VDDO x
0.75
—
—
—
—
V
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer
to the Si5347/46 Family Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
Zs
VOL/VOH
IOL/IOH
IDDO
OUT
OUT
LVCMOS Output Test Configuration
Trace length 5
inches
50
499
0.1 µF
4.7 pF
56
50 Scope Input
499
0.1 µF
50 50 Scope Input
4.7 pF
56
Rev. 1.1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI5347.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| Si5340 | CLOCK GENERATOR | Silicon Laboratories |
| Si5341 | CLOCK GENERATOR | Silicon Laboratories |
| Si5341-40-RM | CLOCK GENERATOR | Silicon Laboratories |
| SI5342 | ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER | Silicon Laboratories |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |