PDF SI5344 Data sheet ( Hoja de datos )

Número de pieza	SI5344
Descripción	ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER
Fabricantes	Silicon Laboratories
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Si5345/44/42 1 0 - C H A N N E L, A N Y- F R E Q U E N C Y, A N Y- O U T P U T J I T T E R A T T E N U A T O R/ C L O C K M U L T I P L I E R Features  Generates any combination of output  frequencies from any input frequency   Input frequency range: Differential: 8 kHz to 750 MHz  LVCMOS: 8 kHz to 250 MHz  Output frequency range:  Differential: up to 712.5 MHz  LVCMOS: up to 250 MHz  Ultra-low jitter: <100 fs typ (12 kHz–20 MHz)  Programmable jitter attenuation  bandwidth from 0.1 Hz to 4 kHz    Meets G.8262 EEC Opt 1, 2 (SyncE) Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML,   and HCSL with programmable signal amplitude   Status monitoring (LOS, OOF, LOL)  Hitless input clock switching: automatic  or manual   Locks to gapped clock inputs   Automatic free-run and holdover  modes  Optional zero delay mode Fastlock feature for low nominal bandwidths Glitchless on the fly output frequency changes DCO mode: as low as 0.001 ppb steps. Core voltage VDD: 1.8 V ±5% VDDA: 3.3 V ±5% Independent output clock supply pins: 3.3 V, 2.5 V, or 1.8 V Output-output skew: 20 ps typ Serial interface: I2C or SPI In-circuit programmable with non-volatile OTP memory ClockBuilder ProTM software simplifies device configuration Si5345: 4 input, 10 output, 64 QFN Si5344: 4 input, 4 output, 44 QFN Si5342: 4 input, 2 output, 44 QFN Temperature range: –40 to +85 °C Pb-free, RoHS-6 compliant Ordering Information: See section 8 Functional Block Diagram Device Selector Guide Grade Si534fA Si534fB Si534fC Si534fD Max Output Frequency 712.5 MHz 350 MHz 712.5 MHz 350 MHz Frequency Synthesis Modes Integer+Fractional Integer+Fractional Integer Integer Applications  OTN Muxponders and Transponders  Carrier Ethernet switches  10/40/100G networking line cards  SONET/SDH Line Cards  GbE/10GbE/100GbE Synchronous  Broadcast video Ethernet (ITU-T G.8262)  Test and measurement  ITU-T G.8262 (SyncE) Compliant Description These jitter attenuating clock multipliers combine fourth-generation DSPLL and MultiSynth™ technologies to enable any-frequency clock generation and jitter attenuation for applications requiring the highest level of jitter performance. These devices are programmable via a serial interface with in-circuit programmable non- volatile memory (NVM) so they always power up with a known frequency configuration. They support free-run, synchronous, and holdover modes of operation, and offer both automatic and manual input clock switching. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level. Programming the Si5345/44/42 is easy with Silicon Labs’ ClockBuilder Pro software. Factory preprogrammed devices are also available. Rev. 1.0 7/15 Copyright © 2015 by Silicon Laboratories Si5345/44/42 1 page Si5345/44/42 Table 2. DC Characteristics (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Core Supply Current Output Buffer Supply Current Total Power Dissipation Symbol IDD IDDA IDDOx Pd Test Condition Si5345 Si5344 Si5342 Si5345 Si5344 Si5342 LVPECL Output4 @ 156.25 MHz LVDS Output4 @ 156.25 MHz 3.3 V LVCMOS5 output @ 156.25 MHz 2.5 V LVCMOS5 output @ 156.25 MHz 1.8 V LVCMOS5 output @ 156.25 MHz Si5345 Notes 1, 6 Si5344 Notes 2, 6 Si5342 Notes 3, 6 Min — — — — — — — — — — — — — — Typ Max Unit 125 185 mA 105 155 mA 105 155 mA 120 125 mA 115 120 mA 115 120 mA 21 25 mA 15 18 mA 21 25 mA 16 18 mA 12 13 mA 880 1040 mW 720 850 mW 715 840 mW Notes: 1. Si5345 test configuration: 10x 3.3 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5344 test configuration: 4x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Si5342 test configuration: 2x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 4. Differential outputs terminated into an AC coupled 100  load. 5. LVCMOS outputs measured into a 6 inch 50  PCB trace with 5 pF load. Measurements were made in CMOS3 mode. 6. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. Rev. 1.0 5 5 Page Si5345/44/42 Table 5. Differential Clock Output Specifications (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Power Supply Noise Rejection4 Symbol Test Condition PSRR Normal Mode 10 kHz sinusoidal noise 100 kHz sinusoidal noise 500 kHz sinusoidal noise 1 MHz sinusoidal noise Min Typ Max Unit — –93 — — –93 — — –84 — — –79 — dBc Low Power Mode 10 kHz sinusoidal noise — –98 — 100 kHz sinusoidal noise — –95 — 500 kHz sinusoidal noise — –84 — 1 MHz sinusoidal noise — –76 — Output-output Crosstalk XTALK Si5345 — –75 — Measured spur from adjacent output5 Si5342/44 — –85 — Measured spur from adjacent output5 dBc dBc dBc Note: 1. For normal and low-power modes, the amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low-power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. Also note that the output voltage swing specifications are given in peak-to-peak single-ended swing. 2. Not all combinations of voltage swing and common mode voltages settings are possible. See the Si5345/44/42 Family Reference Manual for details. 3. Driver output impedance depends on selected output mode (Normal, Low-Power). 4. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and noise spur amplitude measured. 5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk. Rev. 1.0 11 11 Page

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