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PDF MT9M114 Data sheet ( Hoja de datos )
| Número de pieza | MT9M114 | |
| Descripción | 1/6-Inch 720p High-Definition (HD) System-OnA-Chip (SOC) Digital Image Sensor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
1/6-Inch 720p High-Definition (HD) System-On-
A-Chip (SOC) Digital Image Sensor
MT9M114 Datasheet, Rev. 11
For the latest datasheet, please visit www.onsemi.com
Features
• Superior low-light performance
• Ultra-low-power
• 720p HD video at 30 fps
• Internal master clock generated by on-chip
phase-locked loop (PLL) oscillator
• Electronic rolling shutter (ERS), progressive scan
• Integrated image flow processor (IFP) for single-die
camera module
• Automatic image correction and enhancement
• Arbitrary image scaling with anti-aliasing
• Two-wire serial interface providing access to
registers and microcontroller memory
• Selectable output data format: YCbCr, 565RGB,
555RGB, 444RGB, processed Bayer, BT656,
RAW8- and RAW8+2-bit
• Parallel and MIPI data output
• Independently configurable gamma correction
• Adaptive Polynomial lens shading correction
• UVC interface
• Perspective correction
• Multi-camera synchronization
Applications
• Embedded notebook, netbook, and desktop monitor
cameras
• Tethered PC cameras
• Game consoles
• Cell phones, mobile devices, and consumer video
communications
• Surveillance, medical, and industrial applications
General Description
The ON Semiconductor MT9M114 is a 1/6-inch 1.26
Mp CMOS digital image sensor with an active-pixel
array of 1296H x 976V. It includes sophisticated camera
functions such as auto exposure control, auto white
balance, black level control, flicker avoidance, and
defect correction. It is designed for low light perfor-
mance.The MT9M114 produces extraordinarily clear,
sharp digital pictures, making it the perfect choice for
a wide range of applications, including mobile phones,
PC and notebook cameras, and gaming systems.
Table 1:
Key Parameters
Parameter
Optical format
Active pixels
Pixel size
Color filter array
Shutter type
Input clock range
Output pixel clock maximum
Output MIPI data rate maximum
Max. Frame Rate
Responsivity
SNRMAX
Dynamic range
Digital
Analog
Supply voltage I/O
PLL
PHY
Power consumption1
Operating temperature
(ambient) -TA
Chief ray angle
Active imager size
Package options
Typical Value
1/6-inch
1296 x 976= 1.26 Mp
1.9 m x 1.9 m
RGB Bayer
Electronic rolling shutter (ERS)
6 – 54 MHz
96 MHz
768 Mb/s
30 fps full res
36.7 fps 720p
75 fps VGA
120 fps QVGA2
2.24 V/lux-sec(550 nm)
37 dB
70.8 dB
1.7 – 1.95V
2.5 – 3.1V
1.7 – 1.95V or 2.5 – 3.1V
2.5 – 3.1V
1.7 – 1.95V
135 mW
–30°C to +70° C
27.7°
2.46mm (H) x 1.85mm (V),
3.08mm diagonal
Bare die, CSP
Notes: 1. Power consumption for typical voltages and 720p output.
2. Reduced FOV
MT9M114/D Rev. 11, 2/16 EN
1 ©Semiconductor Components Industries, LLC,2016
1 page  
MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Sensor Core
The MT9M114 has a color image sensor with a Bayer color filter arrangement and a
1.2Mp active-pixel array with electronic rolling shutter (ERS). The sensor core readout is
10 bits and can be flipped and/or mirrored. The sensor core also supports separate
analog and digital gain for all four color channels (R, Gr, Gb, B).
Image Flow Processor (IFP)
The advanced IFP features and flexible programmability of the MT9M114 can enhance
and optimize the image sensor performance. Built-in optimization algorithms enable
the MT9M114 to operate with factory settings as a fully automatic and highly adaptable
system-on-a-chip (SOC) for most camera systems.
These algorithms include black level conditioning, shading correction, defect correc-
tion, color interpolation, edge detection, color correction, vertical perspective correc-
tion, aperture correction, and image formatting with cropping and scaling.
Microcontroller Unit (MCU)
The MCU communicates with all functional blocks by way of an internal ON Semicon-
ductor proprietary bus interface. The MCU firmware configures all the registers in the
sensor core and IFP.
System Control
The MT9M114 has a phase-locked loop (PLL) oscillator that can generate the internal
sensor clock from a common wireless system clock. The PLL adjusts the incoming clock
frequency up, allowing the MT9M114 to run at almost any desired resolution and frame
rate within the sensor’s capabilities. Low-power consumption is a very important
requirement.
The MT9M114 provides power-conserving features including a soft standby mode. A
two-wire serial interface bus enables read and write access to the MT9M114’s internal
registers and variables. The internal registers control the sensor core, the color pipeline
flow, and the output interface. Variables are located in the microcontroller's RAM
memory and are used to configure and control the auto-algorithms and camera control
functions.
Output Interface
The output interface block can select either raw data or processed data. Image data is
provided to the host system either by an 8-bit parallel port or by a serial MIPI port. The
parallel output port provides 8-bit RGB data or extended 10-bit Bayer data.
The MT9M114 also includes programmable I/O slew rate to minimize EMI.
System Interfaces
Figure 2 on page 6 shows typical MT9M114 device connections. For low-noise operation,
the MT9M114 requires separate power supplies for analog and digital sections of the die.
Both power supply rails must be decoupled from ground using capacitors as close as
possible to the die. The use of inductance filters is not recommended on the power
supplies or output signals.
The MT9M114 provides dedicated signals for digital core, PHY, and I/O power domains
that can be at different voltages. The PLL and analog circuitry require clean power
sources. Table 3 on page 7 provides the signal descriptions for the MT9M114.
MT9M114/D Rev. 11, 2/16 EN
5 ©Semiconductor Components Industries, LLC,2016.
5 Page 
MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Hard Reset
The MT9M114 enters the reset state when the external RESET_BAR signal is asserted
LOW, as shown in Figure 5. All the output signals will be in High-Z state. When OE_BAR
is in HIGH state, the outputs pins will be High-Z during the internal boot time
Figure 5: Hard Reset Operation
t1
t2 t3
t4
EXTCLK
RESET_BAR
SDATA
All Outputs Data Active
Mode
Reset
Internal Boot Time
Data Active controlled
by OE_BAR
Enter streaming mode
OE_BAR
Table 6: Hard Reset
Symbol
t1
t2
t3
t4
Definition
RESET_BAR pulse width
Active EXTCLK required after RESET_BAR asserted
Active EXTCLK required before RESET_BAR de-asserted
Internal boot time1, 2
Min Typ Max
Unit
50 –
10 –
–
– EXTCLK cycles
10 –
–
– 44.5 –
ms
Notes: 1. 1. Under the condition of EXTCLK=24MHz and default settings with CONFIG=1.
2. The host should poll the Command register to determine when the device is initialized.
MT9M114/D Rev. 11, 2/16 EN
11
©Semiconductor Components Industries, LLC,2016.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT9M114.PDF ] | |
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