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PDF ISL54406 Data sheet ( Hoja de datos )

Número de pieza ISL54406
Descripción Stereo Click and Pop Eliminator
Fabricantes Intersil 
Logotipo Intersil Logotipo



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No Preview Available ! ISL54406 Hoja de datos, Descripción, Manual

Stereo Click and Pop Eliminator with Audio Muting
ISL54406
The Intersil ISL54406 is a Dual SPST (Single Pole/Single
Throw) switch that provides a very low distortion audio
path for a stereo headphone or high impedance line-in
load. This path can be interrupted to provide >110dB of
off-isolation for signal muting purposes into 32Ω or high
impedance loads such as consumer entertainment
system line-inputs, MP3 docking systems for powered
speaker or automotive entertainment system in-line or
cassette interfaces. Recovery from muting is instant
even with very large DC blocking capacitors.
The ISL54406 also has comprehensive Click and Pop
elimination measures to prevent these artifacts from
occurring in the load due to system power-up/power-
down, codec enable/disable, headphone hot plug in,
and audio muting on/off situations. The Click and Pop
elimination is effective into low and high impedance
loads and requires no external timing components to
deal with DC blocking capacitors placed between the
single supply codec and the load.
The ISL54406 is available in a 10 Ld TDFN (3mmx3mm)
or a tiny 10 Ld µTQFN (1.8mmx1.4mm) ultra-thin
package. It operates over a temperature range of -40 to
+85°C.
Features
• Single Supply Operation (VDD) . . . . +2.7V to +5.0V
• Negative Signal Swing Capability . . . . . . . . . . . -1.5V
• Low THD
- THD+N at 1mW into 32Ω Load. . . . . . . . . <0.02%
• Click and Pop Elimination . . . . . . . . . . . . . . . >60dB
• Audio Muting . . . . . . . . . . . . . . . . . . . . . . >110dB
• Low Power Consumption. . . . . . 21µW with 3V supply
• Low Power Shutdown Mode
• 1.8V Logic Compatible
• Available in 10 Ld TDFN (3mmx3mm) or tiny
10 Ld (1.8mmx1.4mm) µTQFN Package
• Pb-Free (RoHS Compliant)
Applications
• Consumer Entertainment Systems
• MP3 and other Personal Media Players
• Cellular/Mobile Phones
• PDA’s
• Audio Switching and Muting
Related Literature*(see page 14)
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”.
• Application Note AN1368 “ISL54406EVAL1Z
Evaluation Board User’s Manual”
Application Block Diagram
3.3V
0.1µF
VDD
LOGIC
CONTROL
LOUT
µCONTROLLER
SEL1
SEL2
LIN
AUDIO
CODEC
ROUT
CLICK AND POP
CIRCUITRY
RIN
ISL54406
GND
July 14, 2010
FN6578.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL54406 pdf
ISL54406
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VSELx_H = 1.4V,
VSELx_L= 0.5V, (Notes 11), Unless Otherwise Specified (Continued)
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
OFF-Isolation, Mute Mode
VDD = 2.7V, VSEL1= 2.7V, RL = 50Ω,
CL = 10pF, (See Figure 1)
VDD = 2.7V, VSEL1= 2.7V, RL = 50Ω,
CL = 10pF, (See Figure 1)
VDD = 3.0V, VSEL2 = 0V, VSEL1= 3.0V,
VLIN or VRIN = 0.707VRMS, RL = 32Ω,
f = 20Hz to 20kHz, (See Figure 3).
+25
+25
+25
-5-
- 45 -
- 110 -
µs
ns
dB
VDD = 3.0V, VSEL2 = 0V, VSEL1= 3.0V,
VLIN or VRIN = 0.707VRMS, RL = 20kΩ,
f = 20Hz to 20kHz, (See Figure 3).
+25
- 110 -
dB
Crosstalk
RIN to LOUT, LIN to ROUT
VDD = 3.0V, VSEL2 = 3.0V, VSEL1= 3.0V,
RL = 32Ω, f = 20Hz to 20kHz, VLIN or
VRIN = 0.707VRMS (2VP-P),
(See Figure 4)
+25
- -90 -
dB
Total Harmonic Distortion
Click and Pop Reduction
(Note 17)
VDD = 3.0V, f = 20Hz to 20kHz,
VSEL2 = 3.0V, VSEL1 = 3.0V, VLIN or
VRIN = 0.36VRMS (1VP-P), RL = 32Ω
VDD = 3.0V, f = 20Hz to 20kHz,
VSEL2 = 3.0V, VSEL1 = 3.0V, VLIN or
VRIN = 0.707VRMS (2VP-P), RL = 32Ω
VDD = 3.0V, VSEL1= 3.0V, VSEL2 = 0V to
3.0V DC step, RL = 20kΩ, VINL or
VINR = 0VDC to 1.5VDC step
(see Figure 6)
+25
+25
+25
- 0.03 -
- 0.06 -
- >60 -
%
%
dB
VDD = 3.0V, VSEL1= 3.0V, VSEL2 = 0V to
3.0V DC step, RL = 32Ω, VINL or
VINR = 0VDC to 1.5VDC step
(see Figure 6)
+25
- >70 -
dB
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
Full 2.7
3.6
Positive Supply Current, IDD VDD = 3.6V, VSEL2 = 1.4V, VSEL1 = 1.4V +25 - 7 10
Full - - 15
V
µA
µA
Shutdown Current, ISHDN VDD = 3.6V, VSEL2 = Float, VSEL1 = Float 25
-
- 50
nA
DIGITAL INPUT CHARACTERISTICS
SELx Voltage Low, VSELx_L VDD = 2.7V to 3.6V
SELx Voltage High, VSELx_H VDD = 2.7V to 3.6V
Input Low Current, ISEL2L, VDD = 3.6V, VSEL2 = 0V or Float,
ISEL1L
VSEL1 = 0V or Float
Full - - 0.5
Full 1.4 -
-
Full -20 2
20
V
V
nA
5 FN6578.1
July 14, 2010

5 Page





ISL54406 arduino
ISL54406
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
2.61
4.0
IOUT = 40mA
3.8
2.60
VDD = 2.7
3.6
3.4
+85°C
2.59
VDD = 3.0
3.2
3.0
IOUT = 40mA
VDD = 3.0V
2.58
VDD = 3.3
2.8
2.6
2.4
+25°C
2.57
VDD = 3.6
2.56
-1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0
VOUT (V)
FIGURE 7. ON-RESISTANCE vs SWITCH VOLTAGE vs
SUPPLY VOLTAGE
2.2
2.0
1.8 -40°C
1.6
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2
VOUT (V)
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE vs
TEMPERATURE
0.068
0.066
RLOAD = 32Ω
VLOAD = 0.707VRMS
0.064
0.062
0.060
VDD = 3.0V
VDD = 3.3V
VDD = 2.7V
VDD = 3.6V
0.10
0.08
0.06
0.04
1.06VRMS
0.884VRMS
0.707VRMS
0.354VRMS
0.058
0.056
20 200 2k 20k
FREQUENCY (Hz)
FIGURE 9. THD+N vs SUPPLY VOLTAGE vs FREQUENCY
0.02
RLOAD = 32Ω
VDD = 3V
RMS VOLTAGES AT LOAD
20 200
2k 20k
FREQUENCY (Hz)
FIGURE 10. THD+N vs SIGNAL LEVELS vs FREQUENCY
0.20
0.10
0.08
0.06
0.04
RLOAD = 32Ω
FREQUENCY = 1kHz
VDD = 3V
0.02
0.01
0.003
0.12 0.23 0.35 0.47 0.58 0.70 0.82 0.93 1.05 1.16
OUTPUT VOLTAGE (VRMS)
FIGURE 11. THD+N vs OUTPUT VOLTAGE
0.10
0.08
0.06
0.04
0.03
0.02
RLOAD = 32Ω
FREQUENCY = 1kHz
VDD = 3V
0.01
0.008
1 2 3 4 5 6 7 8 9 10 20 30
OUTPUT POWER (mW)
FIGURE 12. THD+N vs OUTPUT POWER
11 FN6578.1
July 14, 2010

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