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PDF MSC8102 Data sheet ( Hoja de datos )
| Número de pieza | MSC8102 | |
| Descripción | Packet Telephony Farm Card User Guide | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
User’s Guide
PTKIT8102UG
Rev. 1, 9/2005
MSC8102 Packet Telephony Farm
Card (MSC8102PFC)
The MSC8102 packet telephony farm card (MSC8102PFC) is a
PCI telephony mezzanine card (PTMC) for evaluating media
gateway products. This card is designed around the StarCore™
MSC8102 16-bit fixed-point DSP device. On the MSC8102PFC
is a DSP farm consisting of five MSC8102 devices and one
MSC8101 device to aggregate the data to/from the DSP farm.
Each MSC8102 device has an associated 4M × 32 (16 MB)
SDRAM. The MSC8101 aggregator has a separate 2 M × 32 (8
MB) SDRAM.
The MSC8102PFC interfaces with a baseboard platform via its
PTMC site (see Figure 1). The PTMC is a PCI Mezzanine Card
(PMC) module that conforms to the PMC standard for Jn1 and
Jn2 but uses Jn3 and Jn4 to support a variety of
telecommunications interfaces. The PTMC site on the media
gateway is configured similar to a PT3MC, a subset of the
PTMC specification that supports UTOPIA, Ethernet Reduced
Media-Independent Interface (RMII), and computer telephony
bus interfaces on Jn3/4. An optional fifth connector (Jn5) is
added to support the two MII interfaces supported by the
MSC8101 device. Jn5 is a proprietary connector, effectively
supporting an enhanced PTMC that is backward-compatible
with existing PTMCs.
CONTENTS
1 Packet Telephony Development Kit .......................4
2 Getting Started With the MSC8102PFC .................6
2.1 Board Configuration Options ..................................7
2.2 Flash Memory Programming ..................................9
3 MSC8102PFC Hardware Components ...................9
3.1 MSC8101 Aggregator .............................................9
3.2 MSC8102 DSP Processing Array .........................18
3.3 General Board Configuration ................................24
3.4 MSC8102PFC Board Configuration .....................34
4 Firmware Implementation .....................................35
4.1 MSC8101 Host Memory Controller Settings ........35
4.2 MSC8102 Memory Controller Settings ................37
4.3 MSC8102PFC Reset Configuration Word
(MSC8101) ............................................................38
4.4 MSC8102PFC MSC8102 HRCW .........................38
4.5 MSC8102PFC Bootstrap .......................................39
Data transfer on the board occurs primarily through 10/100
Mbps Ethernet (single RMII or dual MII interfaces) or UTOPIA
and a computer telephony local bus through the PTMC
connectors. Also, an I2C management interface is implemented
through the PTMC J3 connector. Additional I/O interfaces
© Freescale Semiconductor, Inc., 2005. All rights reserved.
1 page  
Packet Telephony Development Kit
Table 2. Reference Documents
Document
Standard Physical and Environmental layers for
PCI Mezzanine Cards: PMC
Standard for a Common Mezzanine Card
Family: CMC
CompactPCI PCI Telecom Mezzanine Card
Specification
H.100 Hardware Compatibility Specification:
CT Bus
Revision
Draft 2.4
Draft 2.4a
R1.0
1.0
Date
Document ID
January 12,
2001
March 21,
2001
April 11, 2001
IEEE: P1386.1
IEEE: P1386
PICMG 2.15
H.100
Freescale Semiconductor
MSC8102 Packet Telephony Farm Card (MSC8102PFC), Rev. 1
5
5 Page 
PSDMR Setting
BSMA = 100
SDA10 = 001
RFRC = 110
PRETOACT = 011
ACTTORW= 011
BL 23 = 1
LDOTOPRE = 10
WRC = 10
EAMUX = 0
BUFCMD = 0
CL = 11
MSC8102PFC Hardware Components
Table 14. MSC8101 PSDMR Settings
Description
A[17–18] are used as bank select signals
A9 maps to the A10/AP pin
Eight clock cycles of refresh recovery
Precharge to activate a 3-cycle interval
Activate to read/write 3 clock cycles
Burst Length is 8
Precharge can be set two cycles before last data is read from
SDRAM
Precharge is set two cycles after the last data is written to SDRAM
External address multiplexing is switched off for fastest timing
Normal timing for the control lines
Cycle CAS Latency = 3
PSDMR = 0xC28737A3: MSC8101 SDRAM
These SDRAM settings are conservative and can be optimized for future configurations and bus frequencies. The
OR and BR settings are described in Table 15.
Table 15. MSC8101 BR and OR Settings
Register Setting
BA = 0x2000_0
PS = 11
MSEL = 010
SDAM= 1111 1111 1000
LSDAM = 0000 0
BPD = 01
ROWST = 1001
NUMR = 010
PMSEL = 0
IBID= 1
Description
Base Address = 0x20000000
32-bit port size
SDRAM machine
BR = 0x20001841
8 MB SDRAM
Four banks per device
Row starts at A9
SDRAM has 11 row lines
Back-to-back page mode (Normal operation)
Bank interleaving disabled
OR = 0xFF803290
After power-on, a JEDEC standard initialization sequence is performed to configure the SDRAM. Software uses
the SDRAM controller PSDMR to perform this task, as follows:
1. Apply power and start the clock. Maintain a No Operation (NOP) condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions at the inputs.
3. Issue a Precharge All command (PALL) to all banks of the device. Program the PSDMR[OP] bits to a
value of 0b101 and then perform an access to the SDRAM bank.
4. Issue eight or more CBR Refresh (REF) commands. Program the PSDMR[OP] bits to a value of 0b001
and then perform eight accesses to the SDRAM bank.
Freescale Semiconductor
MSC8102 Packet Telephony Farm Card (MSC8102PFC), Rev. 1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MSC8102.PDF ] | |
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