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PDF LTC3864 Data sheet ( Hoja de datos )
| Número de pieza | LTC3864 | |
| Descripción | 60V Low IQ Step-Down DC/DC Controller | |
| Fabricantes | Linear Technology | |
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LTC3864
60V Low IQ Step-Down
DC/DC Controller with
100% Duty Cycle Capability
Features
n Wide Operating VIN Range: 3.5V to 60V
n Wide VOUT Range: 0.8V to VIN
n Low Operating IQ = 40µA
n Very Low Dropout Operation: 100% Duty Cycle
n Strong High Voltage MOSFET Gate Driver
n Constant Frequency Current Mode Architecture
n Verified FMEA for Adjacent Pin Open/Short
n Selectable High Efficiency Burst Mode® Operation or
Pulse-Skipping Mode at Light Loads
n Programmable Fixed Frequency: 50kHz to 850kHz
n Phase-Lockable Frequency: 75kHz to 750kHz
n Accurate Current Limit
n Programmable Soft-Start or Voltage Tracking
n Internal Soft-Start Guarantees Smooth Start-Up
n Power Good Output Voltage Monitor
n Low Shutdown IQ = 7µA
n Available in Small 12-Pin Thermally Enhanced MSOP
and DFN Packages
Applications
n Industrial and Automotive Power Supplies
n Telecom Power Supplies
n Distributed Power Systems
Description
The LTC®3864 is a robust, high voltage step-down DC/DC
controller optimized for automotive and industrial applica-
tions. It drives a P-channel power MOSFET switch allowing
100% duty cycle operation. The wide input and output volt-
age ranges cover a multitude of applications. This device
has been verified with the failure mode and effects analysis
(FMEA) procedure for operation during failure conditions.
The LTC3864 offers excellent light load efficiency, draw-
ing only 40µA quiescent current in a user programmable
Burst Mode operation. Its peak current mode, constant
frequency PWM architecture provides for good control of
switching frequency and output current limit. The switch-
ing frequency can be programmed from 50kHz to 850kHz
with an external resistor and can be synchronized to an
external clock from 75kHz to 750kHz.
The LTC3864 offers programmable soft-start or output
tracking. Safety features include overvoltage protection,
overcurrent and short-circuit protection including fre-
quency foldback and a power good output signal.
The LTC3864 is available in thermally enhanced 12-Pin
MSOP and 3mm × 4mm DFN packages.
L, LT, LTC, LTM, OPTI-LOOP, Linear Technology, Burst Mode and the Linear logo are registered
trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5731694.
Typical Application
5.2V to 60V Input, 5V/2A Output, 350kHz Step-Down Converter
0.47µF
VIN*
5.2V TO 60V
10µF
350kHz
3.3nF 9.09k
RUN CAP
VIN
PLLIN/MODE
SS SENSE
LTC3864 GATE
ITH
FREQ
SGND
PGOOD
25mΩ
10µH
100k 422k
VOUT*
5V
2A
47µF
×2
*VOUT FOLLOWS VIN
WHEN 3.5V ≤ VIN ≤ 5.2V
PGND
VFB
80.6k
3864 TA01a
Efficiency
100
Burst Mode
90 OPERATION
80
PULSE-SKIPPING
70
60
50
0.01
VIN = 12V
VOUT = 5V
0.1
LOAD CURRENT (A)
1
3864 TA01b
For more information www.linear.com/LTC3864
3864fa
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1 page  
LTC3864
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
Pulse-Skipping Mode Operation
Waveforms
Burst Mode Operation
Waveforms
Transient Response:
Pulse-Skipping Mode Operation
VOUT
50mV/DIV
VSW
10V/DIV
IL
500mA/DIV
2µs/DIV
VIN = 12V
VOUT = 5V
ILOAD = 100mA
FIGURE 8 CIRCUIT
Transient Response:
Burst Mode Operation
ILOAD
2A/DIV
VOUT
500mV/DIV
IL
2A/DIV
100µs/DIV
VIN = 12V
VOUT = 5V
TRANSIENT = 100mA TO 2A
FIGURE 8 CIRCUIT
Normal Soft Start-Up
VOUT
50mV/DIV
VSW
10V/DIV
ILOAD
2A/DIV
VOUT
500mV/DIV
IL
500mA/DIV
3864 G01
10µs/DIV
VIN = 12V
VOUT = 5V
ILOAD = 100mA
FIGURE 8 CIRCUIT
3864 G02
Dropout Behavior (100% Duty
Cycle)
VIN
2V/DIV
IL
2A/DIV
100µs/DIV
VIN = 12V
VOUT = 5V
TRANSIENT = 100mA TO 2A
FIGURE 8 CIRCUIT
Low VIN Operation
3864 G03
VOUT
2V/DIV
GATE
10V/DIV
VOUT = VIN IN DROPOUT
3864 G04
50ms/DIV
3864 G05
VIN TRANSIENT: 12V TO 4V
AND BACK TO 12V
VOUT = 5V, ILOAD = 100mA, FIGURE 8 CIRCUIT
Soft Start-Up into a Prebiased
Output
VIN
1V/DIV
VOUT
1V/DIV
VOUT PROGRAMMED TO 5V,
BUT STARTS UP IN DROPOUT
SINCE VIN < 5V
SW
5V/DIV
20ms/DIV
VIN = 0V TO 3.8V
THEN BACK TO 0V
ILOAD = 100mA
FIGURE 8 CIRCUIT
Output Tracking
3864 G06
VIN
5V/DIV
SS
200mV/DIV
VOUT
1V/DIV
1ms/DIV
VIN = 12V, VOUT = 5V
FIGURE 8 CIRCUIT
RUN
5V/DIV
VOUT
1V/DIV
SS
200mV/DIV
VOUT PREBIASED
TO 2.9V
3864 G07
1ms/DIV
VIN = 12V, VOUT = 5V
ILOAD = 0.5mA
FIGURE 8 CIRCUIT
SS
200mV/DIV
VOUT
2V/DIV
3864 G08
20ms/DIV
VIN = 12V, VOUT = 5V
ILOAD = 100mA
FIGURE 8 CIRCUIT
For more information www.linear.com/LTC3864
3864 G09
3864fa
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5 Page 
Operation
the internal sleep signal goes high, enabling sleep mode.
The ITH pin is then disconnected from the output of the
error amplifier and held at 0.55V.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current to 40µA while the load
current is supplied by the output capacitor. As the output
voltage and hence the feedback voltage decreases, the
error amplifier’s output will rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the error amplifier, the sleep signal goes low, and the
controller resumes normal operation by turning on the
external P-MOSFET on the next cycle of the internal oscil-
lator. In Burst Mode operation, the peak inductor current
has to reach at least 25% of current limit for the current
comparator, ICMP, to trip and turn the P-MOSFET back off,
even though the ITH voltage may indicate a lower current
setpoint value.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3864 will skip pulses during light loads. In
this mode, ICMP may remain tripped for several cycles and
force the external MOSFET to stay off, thereby skipping
pulses. This mode offers the benefits of smaller output
ripple, lower audible noise, and reduced RF interference,
at the expense of lower efficiency when compared to Burst
Mode operation.
Frequency Selection and Clock Synchronization
The switching frequency of the LTC3864 can be selected
using the FREQ pin. If the PLLIN/MODE pin is not being
driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through an
external resistor. Tying FREQ pin to signal ground selects
350kHz, while floating selects 535kHz. Placing a resistor
between FREQ pin and signal ground allows the frequency
to be programmed between 50kHz and 850kHz.
The phase-locked loop (PLL) on the LTC3864 will syn-
chronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
the turn-on edge of the external P-channel MOSFET to be
aligned with the rising edge of the synchronizing signal.
LTC3864
The oscillator’s default frequency is based on the operating
frequency set by the FREQ pin. If the oscillator’s default
frequency is near the external clock frequency, only slight
adjustments are needed for the PLL to synchronize the
external P-channel MOSFET’s turn-on edge to the rising
edge of the external clock. This allows the PLL to lock
rapidly without deviating far from the desired frequency.
The PLL is guaranteed from 75kHz to 750kHz. The clock
input levels should be greater than 2V for HI and less
than 0.5V for LO.
Power Good and Fault Protection
The PGOOD pin is an open-drain output. An internal
N-channel MOSFET pulls the PGOOD pin low when the VFB
pin voltage is outside a ±10% window from the 0.8V internal
voltage reference. The PGOOD pin is also pulled low when
the RUN pin is low (shut down). When the VFB pin voltage
is within the ±10% window, the MOSFET is turned off and
the pin is allowed to be pulled up by an external resistor
to a source no greater than 6V. The PGOOD open-drain
output has a 100µs delay before it can transition states.
When the VFB voltage is above +10% of the regulated
voltage of 0.8V, this is considered as an overvoltage con-
dition and the external P-MOSFET is immediately turned
off and prevented from ever turning on until VFB returns
below +7.5%.
In the event of an output short circuit or overcurrent con-
dition that causes the output voltage to drop significantly
while in current limit, the LTC3864 operating frequency
will fold back. Anytime the output feedback VFB voltage is
less than 50% of the 0.8V internal reference (i.e., 0.4V),
frequency foldback is active. The frequency will continue
to drop as VFB drops until reaching a minimum foldback
frequency of about 18% of the setpoint frequency. Fre-
quency foldback is designed, in combination with peak
current limit, to limit current in start-up and short-circuit
conditions. Setting the foldback frequency as a percentage
of operating frequency assures that start-up characteristics
scale appropriately with operating frequency.
For more information www.linear.com/LTC3864
3864fa
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3864.PDF ] | |
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