DataSheet.es    


PDF STM32F103ZF Data sheet ( Hoja de datos )

Número de pieza STM32F103ZF
Descripción XL-density performance line ARM-based 32-bit MCU
Fabricantes STMicroelectronics　
Logotipo STMicroelectronics Logotipo



Hay una vista previa y un enlace de descarga de STM32F103ZF (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! STM32F103ZF Hoja de datos, Descripción, Manual

STM32F103xF
STM32F103xG
XL-density performance line ARM-based 32-bit MCU with 768 KB to
1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces
Target specification
Features
■ Core: ARM 32-bit Cortex™-M3 CPU with MPU
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
■ Memories
– 768 Kbytes to 1 Mbyte of Flash memory
– 96 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
■ Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
■ Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
■ 3 × 12-bit, 1 µs A/D converters (up to 21
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
■ 2 × 12-bit D/A converters
■ DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
SDIO, I2Ss, SPIs, I2Cs and USARTs
■ Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
FBGA
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
LFBGA144 10 × 10 mm
■ Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
■ Up to 17 timers
– Up to ten 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 × 16-bit motor control PWM timers with
dead-time generation and emergency stop
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
■ Up to 13 communication interfaces
– Up to 2 × I2C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I2S
interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
■ CRC calculation unit, 96-bit unique ID
■ ECOPACK® packages
Table 1. Device summary
Reference
Part number
STM32F103xF
STM32F103RF STM32F103VF
STM32F103ZF
STM32F103xG
STM32F103RG STM32F103VG
STM32F103ZG
January 2012
Doc ID 16554 Rev 3
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/120
www.st.com
1

1 page




STM32F103ZF pdf
STM32F103xF, STM32F103xG
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F103xF and STM32F103xG features and peripheral counts . . . . . . . . . . . . . . . . . 11
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F103xF and STM32F103xG timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19
STM32F103xF and STM32F103xG pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 46
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 47
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 63
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 64
Asynchronous read muxed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 71
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Switching characteristics for PC Card/CF read and write cycles in
attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . 78
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Doc ID 16554 Rev 3
5/120

5 Page





STM32F103ZF arduino
STM32F103xF, STM32F103xG
Description
2.1
Device overview
The STM32F103xx XL-density performance line family offers devices in four different
package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
Figure 1 shows the general block diagram of the device family.
Table 2. STM32F103xF and STM32F103xG features and peripheral counts
Peripherals
STM32F103Rx
STM32F103Vx
STM32F103Zx
Flash memory
SRAM in Kbytes
FSMC
General-purpose
Timers Advanced-control
Basic
SPI(I2S)(2)
I2C
USART
Comm
USB
CAN
SDIO
GPIOs
12-bit ADC
Number of channels
12-bit DAC
Number of channels
CPU frequency
Operating voltage
Operating temperatures
Package
768 KB
1 MB
768 KB
1 MB
768 KB
1 MB
96 96 96
No
Yes(1)
Yes
10
2
2
3(2)
2
5
1
1
1
51 80 112
3 33
16 16 21
2
2
72 MHz
2.0 to 3.6 V
Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10)
Junction temperature: –40 to + 125 °C (see Table 10)
LQFP64
LQFP100
LQFP144, BGA144
1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a
multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND
Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available
in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the
I2S audio mode.
Doc ID 16554 Rev 3
11/120

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet STM32F103ZF.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
STM32F103ZCARM-based 32-bit MCUSTMicroelectronics
STMicroelectronics
STM32F103ZDARM-based 32-bit MCUSTMicroelectronics
STMicroelectronics
STM32F103ZEARM-CM3 Board User ManualEMBEST
EMBEST
STM32F103ZEARM-CM3 Board Getting StartedEMBEST
EMBEST

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

 Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

 Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar