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PDF ISL6614 Data sheet ( Hoja de datos )
| Número de pieza | ISL6614 | |
| Descripción | Dual Advanced Synchronous Rectified Buck MOSFET Drivers | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
Dual Advanced Synchronous Rectified
Buck MOSFET Drivers with Protection
Features
The ISL6614 integrates two ISL6613 MOSFET drivers and is
specifically designed to drive two independent power
channels in a Multi-Phase interleaved buck converter
topology. These drivers combined with HIP63xx or ISL65xx
Multi-Phase Buck PWM controllers and N-Channel
MOSFETs form complete core-voltage regulator solutions for
advanced microprocessors.
The ISL6614 drives both the upper and lower gates
simultaneously over a range from 5V to 12V. This drive
voltage provides the flexibility necessary to optimize
applications involving trade-offs between gate charge and
conduction losses.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during startup. The over-
temperature protection feature prevents failures resulting
from excessive power dissipation by shutting off the outputs
when its junction temperature exceeds +150°C (typically).
The driver resets once its junction temperature returns to
+108°C (typically).
The ISL6614 also features a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
ISL6614
May 5, 2008
FN9155.5
Features
• Pin-to-pin Compatible with HIP6602 SOIC Family for
Better Performance and Extra Protection Features
• Quad N-Channel MOSFET Drives for Two Synchronous
Rectified Bridges
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage +Protection
• VCC Undervoltage Protection
• Over-Temperature Protection (OTP) with +42°C Hysteresis
• Expandable Bottom Copper Pad for Enhanced Heat Sinking
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and has a Thinner Profile
• Pb-free Available (RoHS compliant)
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief 400 and 417 for Power Train Design,
Layout Guidelines, and Feedback Compensation Design
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6614
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND <36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance (Typical) . . . . . . . . . . θJA(°C/W) θJC(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
90
N/A
QFN Package (Notes 2, 3). . . . . . . . . .
44
4.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V ±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
IVCC
IPVCC
fPWM = 300kHz, VPVCC = 12V
fPWM = 300kHz, VPVCC = 12V
- 7.1 - mA
- 9.7 - mA
VCC Rising Threshold
0°C to +85°C
9.35 9.80 10.05
V
-40°C to +85°C
8.35 - 10.05 V
VCC Falling Threshold
0°C to +85°C
7.35 7.60 8.00
V
-40°C to +85°C
6.35 - 8.00 V
PWM INPUT (See “TIMING DIAGRAM” on page 8)
Input Current
PWM Rising Threshold
PWM Falling Threshold
Typical Three-State Shutdown Window
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Upper Gate Rising Threshold
Three-State Upper Gate Falling Threshold
Shutdown Hold-off Time
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Propagation Delay (Note 4)
IPWM
tTSSHD
tRU
tRL
tFU
tFL
tPDHU
VPWM = 5V
VPWM = 0V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VPVCC = 12V, 3nF Load, 10% to 90%
VPVCC = 12V, 3nF Load, 10% to 90%
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, Adaptive
-
-
-
-
1.80
-
-
-
-
-
-
-
-
-
-
450
-400
3.00
2.00
-
1.50
1.00
3.20
2.60
245
26
18
18
12
10
-
-
-
-
2.40
-
-
-
-
-
-
-
-
-
-
µA
µA
V
V
V
V
V
V
V
ns
ns
ns
ns
ns
ns
5 FN9155.5
May 5, 2008
5 Page 
ISL6614
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A 0.80 0.90 1.00 -
A1 -
- 0.05 -
A2 -
- 1.00 9
A3 0.20 REF 9
b 0.23 0.28 0.35 5, 8
D
4.00 BSC
-
D1 3.75 BSC 9
D2 1.95 2.10 2.25 7, 8
E
4.00 BSC
-
E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8
e
0.65 BSC
-
k 0.25
-
--
L 0.50 0.60 0.75 8
L1 -
- 0.15 10
N 16 2
Nd 4 3
Ne 4 3
P-
- 0.60 9
θ-
- 12 9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
11 FN9155.5
May 5, 2008
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL6614.PDF ] | |
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