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PDF TSL2563 Data sheet ( Hoja de datos )

Número de pieza TSL2563
Descripción LOW-VOLTAGE LIGHT-TO-DIGITAL CONVERTER
Fabricantes TAOS 
Logotipo TAOS Logotipo



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r
r
D Approximates Human Eye Response
D Programmable Interrupt Function with
User-Defined Upper and Lower Threshold
Settings
D 16-Bit Digital Output with SMBus (TSL2562)
at 100 kHz or I2C (TSL2563) Fast-Mode at
400 kHz
D Programmable Analog Gain and Integration
Time Supporting 1,000,000-to-1 Dynamic
Range
D Automatically Rejects 50/60-Hz Lighting
Ripple
D Low 2.5-V Input Voltage and 1.8-V Digital
Output
D Low Active Power (0.6 mW Typical) with
Power Down Mode
D RoHS Compliant
TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066N − AUGUST 2010
PACKAGE CS
6-LEAD CHIPSCALE
(TOP VIEW)
VDD 1
ADDR SEL 2
GND 3
6 SDA
5 INT
4 SCL
VDD 1
ADDR SEL 2
GND 3
PACKAGE T
6-LEAD TMB
(TOP VIEW)
6 SDA
5 INT
4 SCL
Description
The TSL2562 and TSL2563 are low-voltage
light-to-digital converters that transform light
intensity to a digital signal output capable of direct
I2C (TSL2563) or SMBus (TSL2562) interface.
Each device combines one broadband photo-
diode (visible plus infrared) and one infrared-re-
sponding photodiode on a single CMOS inte-
grated circuit capable of providing a near-photop-
ic response over an effective 20-bit dynamic
range (16-bit resolution). Two integrating ADCs
convert the photodiode currents to a digital output
that represents the irradiance measured on each
channel. This digital output can be input to a
microprocessor where illuminance (ambient light
level) in lux is derived using an empirical formula
to approximate the human eye response. The
TSL2562 device permits an SMB-Alert style
interrupt, and the TSL2563 device supports a
traditional level style interrupt that remains
asserted until the firmware clears it.
PACKAGE FN
DUAL FLAT NO-LEAD
(TOP VIEW)
VDD 1
ADDR SEL 2
GND 3
6 SDA
5 INT
4 SCL
SDA 5
PACKAGE CL
6-LEAD ChipLED
(TOP VIEW)
4 SCL
INT 6
3 ADDR SEL
VDD 1
2 GND
Package Drawings are Not to Scale
While useful for general purpose light sensing applications, the TSL2562/63 devices are designed particularly
for display panels (LCD, OLED, etc.) with the purpose of extending battery life and providing optimum viewing
in diverse lighting conditions. Display panel backlighting, which can account for up to 30 to 40 percent of total
platform power, can be automatically managed. Both devices are also ideal for controlling keyboard illumination
based upon ambient lighting conditions. Illuminance information can further be used to manage exposure
control in digital cameras. The TSL2562/63 devices are ideal in notebook/tablet PCs, LCD monitors, flat-panel
televisions, cell phones, and digital cameras. In addition, other applications include street light control, security
lighting, sunlight harvesting, machine vision, and automotive instrumentation clusters.
The LUMENOLOGY r Company
r
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972r) 673-0759
www.taosinc.com
Copyright E 2010, TAOS Inc.
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TSL2563 pdf
TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066N − AUGUST 2010
NOTES: 2. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDs
and infrared 940 nm LEDs are used for final product testing for compatibility with high-volume production.
3. The 640 nm irradiance Ee is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength
λp = 640 nm and spectral halfwidth Δλ½ = 17 nm.
4. The 940 nm irradiance Ee is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelength
λp = 940 nm and spectral halfwidth Δλ½ = 40 nm.
5. Integration time Tint, is dependent on internal oscillator frequency (fosc) and on the integration field value in the timing register as
described in the Register Set section. For nominal fosc = 735 kHz, nominal Tint = (number of clock cycles)/fosc.
Field value 00: Tint = (11 × 918)/fosc = 13.7 ms
Field value 01: Tint = (81 × 918)/fosc = 101 ms
Field value 10: Tint = (322 × 918)/fosc = 402 ms
Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01),
and 322/322 = 1 (field value 10).
6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also
by a 2-count offset.
Full scale ADC count value = ((number of clock cycles)/2 − 2)
Field value 00: Full scale ADC count value = ((11 × 918)/2 − 2) = 5047
Field value 01: Full scale ADC count value = ((81 × 918)/2 − 2) = 37177
Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached
for 131074 clock cycles, which occurs for Tint = 178 ms for nominal fosc = 735 kHz.
7. Low gain mode has 16y lower gain than high gain mode: (1/16 = 0.0625).
8. The sensor Lux is calculated using the empirical formula shown on p. 22 of this data sheet based on measured Ch0 and Ch1 ADC
count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual
Lux) ratio is estimated based on the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with
fluorescent or incandescent light sources.
The LUMENOLOGY r Company
r
www.taosinc.com
r
Copyright E 2010, TAOS Inc.
5

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TSL2563 arduino
TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066N − AUGUST 2010
When an SMBus Block Write or Block Read is initiated (see description of COMMAND Register), the byte
following the COMMAND byte is ignored but is a requirement of the SMBus specification. This field contains
the byte count (i.e. the number of bytes to be transferred). The TSL2562 (SMBus) device ignores this field and
extracts this information by counting the actual number of bytes transferred before the Stop condition is
detected.
When an I2C Write or I2C Read (Combined Format) is initiated, the byte count is also ignored but follows the
SMBus protocol specification. Data bytes continue to be transferred from the TSL2563 (I2C) device to Master
until a NACK is sent by the Master.
The data formats supported by the TSL2562 and TSL2563 devices are:
D Master transmitter transmits to slave receiver (SMBus and I2C):
− The transfer direction in this case is not changed.
D Master reads slave immediately after the first byte (SMBus only):
− At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter
becomes a master receiver and the slave receiver becomes a slave transmitter.
D Combined format (SMBus and I2C):
− During a change of direction within a transfer, the master repeats both a START condition and the slave
address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and a STOP condition.
For a complete description of SMBus protocols, please review the SMBus Specification at
http://www.smbus.org/specs. For a complete description of I2C protocols, please review the I2C Specification
at http://www.semiconductors.philips.com.
17
S Slave Address
11
Wr A
X
8
Data Byte
11
AP
X
A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)
P Stop Condition
Rd Read (bit value of 1)
S Start Condition
Sr Repeated Start Condition
Wr Write (bit value of 0)
X Shown under a field indicates that that field is required to have a value of X
... Continuation of protocol
Master-to-Slave
Slave-to-Master
Figure 9. SMBus and I2C Packet Protocol Element Key
The LUMENOLOGY r Company
r
www.taosinc.com
r
Copyright E 2010, TAOS Inc.
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