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PDF TSL2569 Data sheet ( Hoja de datos )
| Número de pieza | TSL2569 | |
| Descripción | LIGHT-TO-DIGITAL CONVERTER | |
| Fabricantes | TAOS | |
| Logotipo |  |
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D Approximates Human Eye Response
D Approximately 4y More Sensitive Than
TSL2560/61 Device
D Programmable Interrupt Function with
User-Defined Upper and Lower Threshold
Settings
D 16-Bit Digital Output with SMBus (TSL2568)
at 100 kHz or I2C (TSL2569) Fast-Mode at
400 kHz
D Programmable Analog Gain and Integration
Time Supporting 1,000,000-to-1 Dynamic
Range
D Available in Ultra-Small 1.25 mm y 1.75 mm
Chipscale Package
D Automatically Rejects 50/60-Hz Lighting
Ripple
D Low Active Power (0.75 mW Typical) with
Power Down Mode
D RoHS Compliant
TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
PACKAGE CS
6-LEAD CHIPSCALE
(TOP VIEW)
VDD 1
ADDR SEL 2
GND 3
6 SDA
5 INT
4 SCL
Package Drawings are Not to Scale
PACKAGE T
6-LEAD TMB
(TOP VIEW)
VDD 1
ADDR SEL 2
GND 3
6 SDA
5 INT
4 SCL
Description
The TSL2568 and TSL2569 are high-sensitivity light-to-digital converters that transform light intensity to a digital
signal output capable of direct I2C (TSL2569) or SMBus (TSL2568) interface. Each device combines one
broadband photodiode (visible plus infrared) and one infrared-responding photodiode on a single CMOS
integrated circuit capable of providing a near-photopic response over an effective 20-bit dynamic range (16-bit
resolution). Two integrating ADCs convert the photodiode currents to a digital output that represents the
irradiance measured on each channel. This digital output can be input to a microprocessor where illuminance
(ambient light level) in lux is derived using an empirical formula to approximate the human eye response. The
TSL2568 device permits an SMB-Alert style interrupt, and the TSL2569 device supports a traditional level style
interrupt that remains asserted until the firmware clears it.
While useful for general purpose light sensing applications, the TSL2568/69 devices are designed particularly
for display panels (LCD, OLED, etc.) with the purpose of extending battery life and providing optimum viewing
in diverse lighting conditions. Display panel backlighting, which can account for up to 30 to 40 percent of total
platform power, can be automatically managed. Both devices are also ideal for controlling keyboard illumination
based upon ambient lighting conditions. Illuminance information can further be used to manage exposure
control in digital cameras. The TSL2568/69 devices are ideal in notebook/tablet PCs, LCD monitors, flat-panel
televisions, cell phones, and digital cameras. In addition, other applications include street light control, security
lighting, sunlight harvesting, machine vision, and automotive instrumentation clusters.
The LUMENOLOGY r Company
r
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972r) 673-0759
www.taosinc.com
Copyright E 2008, TAOS Inc.
1
1 page  
TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
NOTES: 2. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDs
and infrared 940 nm LEDs are used for final product testing for compatibility with high-volume production.
3. The 640 nm irradiance Ee is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength
λp = 640 nm and spectral halfwidth Δλ½ = 17 nm.
4. The 940 nm irradiance Ee is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelength
λp = 940 nm and spectral halfwidth Δλ½ = 40 nm.
5. Integration time Tint, is dependent on internal oscillator frequency (fosc) and on the integration field value in the timing register as
described in the Register Set section. For nominal fosc = 735 kHz, nominal Tint = (number of clock cycles)/fosc.
Field value 00: Tint = (11 × 918)/fosc = 13.7 ms
Field value 01: Tint = (81 × 918)/fosc = 101 ms
Field value 10: Tint = (322 × 918)/fosc = 402 ms
Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01),
and 322/322 = 1 (field value 10).
6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also
by a 2-count offset.
Full scale ADC count value = ((number of clock cycles)/2 − 2)
Field value 00: Full scale ADC count value = ((11 × 918)/2 − 2) = 5047
Field value 01: Full scale ADC count value = ((81 × 918)/2 − 2) = 37177
Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached
for 131074 clock cycles, which occurs for Tint = 178 ms for nominal fosc = 735 kHz.
7. Low gain mode has 16y lower gain than high gain mode: (1/16 = 0.0625).
8. The sensor Lux is calculated using the empirical formula shown on p. 22 of this data sheet based on measured Ch0 and Ch1 ADC
count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual
Lux) ratio is estimated based on the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with
fluorescent or incandescent light sources.
AC Electrical Characteristics, VDD = 3 V, TA = 255C (unless otherwise noted)
PARAMETER†
TEST CONDITIONS
MIN
t(CONV)
f(SCL)
Conversion time
Clock frequency (I2C only)
Clock frequency (SMBus only)
12
0
10
t(BUF)
Bus free time between start and stop condition
1.3
t(HDSTA)
Hold time after (repeated) start condition. After
this period, the first clock is generated.
0.6
t(SUSTA)
Repeated start condition setup time
t(SUSTO)
Stop condition setup time
t(HDDAT)
Data hold time
t(SUDAT)
Data setup time
t(LOW)
SCL clock low period
t(HIGH)
SCL clock high period
t(TIMEOUT) Detect clock/data low timeout (SMBus only)
tF Clock/data fall time
tR Clock/data rise time
Ci Input pin capacitance
† Specified by design and characterization; not production tested.
0.6
0.6
0
100
1.3
0.6
25
TYP
100
MAX
400
400
100
UNIT
ms
kHz
kHz
μs
μs
μs
μs
0.9 μs
ns
μs
μs
35 ms
300 ns
300 ns
10 pF
The LUMENOLOGY r Company
r
www.taosinc.com
r
Copyright E 2008, TAOS Inc.
5
5 Page 
TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
1 7 11
S Slave Address Wr A
8
Command Code
1
A
8
Byte Count = N
1
A
TAOS091D − DECEMBER 2008
8
Data Byte 1
1
A ...
8
Data Byte 2
1
A ...
8
Data Byte N
11
AP
Figure 14. SMBus Block Write or I2C Write Protocols
NOTE: The I2C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
1 7 11
S Slave Address Wr A
8
Command Code
11 7 11
A Sr Slave Address Rd A
8
Byte Count = N
1
A ...
8
Data Byte 1
1
A
8
Data Byte 2
1
A ...
8
Data Byte N
11
AP
1
Figure 15. SMBus Block Read or I2C Read (Combined Format) Protocols
NOTE: The I2C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates
a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
Register Set
The TSL256x is controlled and monitored by sixteen registers (three are reserved) and a command register
accessed through the serial interface. These registers provide for a variety of control functions and can be read
to determine results of the ADC conversions. The register set is summarized in Table 2.
Table 2. Register Address
ADDRESS
−−
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
RESISTER NAME
COMMAND
CONTROL
TIMING
THRESHLOWLOW
THRESHLOWHIGH
THRESHHIGHLOW
THRESHHIGHHIGH
INTERRUPT
−−
CRC
−−
ID
−−
DATA0LOW
DATA0HIGH
DATA1LOW
DATA1HIGH
REGISTER FUNCTION
Specifies register address
Control of basic functions
Integration time/gain control
Low byte of low interrupt threshold
High byte of low interrupt threshold
Low byte of high interrupt threshold
High byte of high interrupt threshold
Interrupt control
Reserved
Factory test — not a user register
Reserved
Part number/ Rev ID
Reserved
Low byte of ADC channel 0
High byte of ADC channel 0
Low byte of ADC channel 1
High byte of ADC channel 1
The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section
on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status
register for following read/write operations.
The LUMENOLOGY r Company
r
Copyright E 2008, TAOS Inc.
www.taosinc.com
r
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TSL2569.PDF ] | |
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