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PDF CS4207 Data sheet ( Hoja de datos )

Número de pieza CS4207
Descripción Low-power 4-in 6-out HD Audio Codec
Fabricantes Cirrus Logic　
Logotipo Cirrus Logic Logotipo



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CS4207
Low-power, 4-in / 6-out HD Audio Codec with Headphone Amp
DIGITAL to ANALOG FEATURES
DAC1 (Headphone)
– 101 dB Dynamic Range (A-wtd)
– -89 dB THD+N
Headphone Amplifier - GND Centered
– Integrated Negative-voltage Regulator
– No DC-blocking Capacitor Required
– 50 mW Power/Channel into 16
DAC2 & DAC3 (Line Outs)
– 110 dB Dynamic Range (A-wtd)
– -94 dB THD+N
– Differential Balanced or Single-ended
Each DAC Supports 32 kHz to 192 kHz Sample
Rates Independently.
Digital Volume Control
– +6.0 dB to -57.5 dB in 0.5 dB Steps
– Zero Cross and/or Soft Ramp Transitions
Independent Support of D0 and D3 Power
States for Each DAC
Fast D3 to D0 Transition
– Audio Playback in Less Than 50 ms
ANALOG to DIGITAL FEATURES
ADC1 & ADC2
– 105 dB Dynamic Range (A-wtd)
– -88 dB THD+N
– Differential Balanced or Single-ended
Inputs
– Analog Programmable Gain Amplifier
(PGA) ±12 dB, 1.0 dB Steps, with Zero
Cross Transitions and Mute
MIC Inputs
– Pre-amplifier with Selectable 0 dB, +10 dB,
+20 dB, and +30 dB Gain Settings
– Programmable, Low-noise MIC Bias Level
Each ADC Supports 8 kHz to 96 kHz Sample
Rates Independently
Additional Digital Attenuation Control
– -13.0 dB to -51.0 dB in 1.0 dB steps
– Zero Cross and/or Soft Ramp Transitions
Digital Interface for Two Dual Digital Mic Inputs
Independent Support of D0 and D3 Power
States for Each ADC
HD Audio
Bus
VL_HD
(1.5 V to 3.3 V)
GPIO
S/PDIF OUT 2
S/PDIF OUT 1
VL_IF
(3.3 V)
S/PDIF IN
D-Mic Clock
D-Mic In
VD
(1.5 V to 1.8 V)
HD
Audio
Interface
GPIO
SPDIF
TX2
SPDIF
TX1
HD Bus
Fs
128Fs Clock
Multiplier
SPDIF
RX
SPDIF
RX SRC
Vol/Mute
Vol/Mute
Vol/Mute
Vol/Boost/
Mute
Vol/Boost/
Mute
SRC &
Multibit 
Modulator
SRC &
Multibit 
Modulator
SRC &
Multibit 
Modulator
Digital
Filter &
SRC
Digital
Filter &
SRC
VA, VA_REF
(3.3 V to 5.0 V)
2-Chnl
DAC1
2-Chnl
DAC2
2-Chnl
DAC3
2-Chnl
ADC1
2-Chnl
ADC2
Jack
Sense
VA_HP
(3.3 V to 5.0 V)
Chrg
Pump
Buck
Chrg
Pump
Invert
+VHP
-VHP
Headphone
Amp - GND
Centered
Left HP Out
Right HP Out
Line +- Left Line Out
Out +- Right Line Out
Line +- Left Line Out
Out +- Right Line Out
PGA
+
- Line/Mic In L
Line/Mic In R
+
PGA
MIC
Bias
+- Mic/Line In L
+- Mic/Line In R
Mic Bias
SENSE_A
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
AUG '12
DS880F4

1 page




CS4207 pdf
CS4207
6.8.7 Pin Widget Control ................................................................................................................ 81
6.8.8 Unsolicited Response Control ............................................................................................... 82
6.8.9 Pin Sense .............................................................................................................................. 83
6.8.10 Configuration Default ........................................................................................................... 83
6.9 Line Out 1 Pin Widget (Node ID = 0Ah) ......................................................................................... 85
6.9.1 Audio Widget Capabilities ..................................................................................................... 85
6.9.2 Pin Capabilities ...................................................................................................................... 86
6.9.3 Connection List Length .......................................................................................................... 86
6.9.4 Supported Power States ....................................................................................................... 87
6.9.5 Connection List Entry ............................................................................................................ 87
6.9.6 Power States ......................................................................................................................... 87
6.9.7 Pin Widget Control ................................................................................................................ 88
6.9.8 Unsolicited Response Control ............................................................................................... 89
6.9.9 Pin Sense .............................................................................................................................. 90
6.9.10 EAPD/BTL Enable ............................................................................................................... 90
6.9.11 Configuration Default ........................................................................................................... 91
6.10 Line Out 2 Pin Widget (Node ID = 0Bh) ....................................................................................... 92
6.10.1 Audio Widget Capabilities ................................................................................................... 92
6.10.2 Pin Capabilities .................................................................................................................... 93
6.10.3 Connection List Length ........................................................................................................ 93
6.10.4 Connection List Entry .......................................................................................................... 94
6.10.5 Pin Widget Control .............................................................................................................. 94
6.10.6 EAPD/BTL Enable ............................................................................................................... 95
6.10.7 Configuration Default ........................................................................................................... 96
6.11 Line In 1/Mic In 2, Mic In 1/Line In 2 Pin Widgets (Node ID = 0Ch, 0Dh) .................................... 97
6.11.1 Audio Widget Capabilities ................................................................................................... 97
6.11.2 Line In 1/Mic In 2 Pin Capabilities ....................................................................................... 97
6.11.3 Mic In 1/Line In 2 Pin Capabilities ....................................................................................... 98
6.11.4 Input Amplifier Capabilities .................................................................................................. 99
6.11.5 Supported Power States ..................................................................................................... 99
6.11.6 Power States ....................................................................................................................... 99
6.11.7 Line In 1/Mic In 2 Pin Widget Control ................................................................................ 101
6.11.8 Mic In 1/Line In 2 Pin Widget Control ................................................................................ 101
6.11.9 Unsolicited Response Control ........................................................................................... 102
6.11.10 Pin Sense ........................................................................................................................ 103
6.11.11 Mic In 1/Line In 2 EAPD/BTL Enable .............................................................................. 104
6.11.12 Line In 1/Mic In 2 Configuration Default .......................................................................... 104
6.11.13 Mic In 1/Line In 2 Configuration Default .......................................................................... 105
6.11.14 Amplifier Gain/Mute ......................................................................................................... 106
6.12 Digital Mic In 1, Digital Mic In 2 Pin Widgets (Node ID = 0Eh, 12h) ........................................... 108
6.12.1 Audio Widget Capabilities ................................................................................................. 108
6.12.2 Pin Capabilities .................................................................................................................. 109
6.12.3 Input Amplifier Capabilities ................................................................................................ 109
6.12.4 Pin Widget Control ............................................................................................................ 110
6.12.5 Digital Mic In 1 Configuration Default ................................................................................ 110
6.12.6 Digital Mic In 2 Configuration Default ................................................................................ 111
6.12.7 Amplifier Gain/Mute ........................................................................................................... 112
6.13 S/PDIF Receiver Input Pin Widget (Node ID = 0Fh) .................................................................. 114
6.13.1 Audio Widget Capabilities ................................................................................................. 114
6.13.2 Pin Capabilities .................................................................................................................. 115
6.13.3 Supported Power States ................................................................................................... 115
6.13.4 Power States ..................................................................................................................... 116
6.13.5 Pin Widget Control ............................................................................................................ 117
6.13.6 Unsolicited Response Control ........................................................................................... 117
DS880F4
5

5 Page





CS4207 arduino
2. TYPICAL CONNECTION DIAGRAMS
CS4207
+5.0 V
0.1 µF
0.1 µF
+1.8 V
+5.0 V
0.1 µF + 10 µF
+5.0 V
0.1 µF **10 µF **10 µF
** 2.2 µF
** 2.2 µF
** Use low ESR
ceramic capacitors.
HD Audio
Bus
+1.5 V to +3.3 V
0.1 µF
VA
VA_REF
VD
VBIAS
HPOUT_L
HPREF
CS4207
VA_HP
VHP_FILT+
HPOUT_R
VHP_FILT-
FLYP
FLYC
FLYN
LINEOUT_L1+
LINEOUT_L1-
LINEOUT_R1+
LINEOUT_R1-
BITCLK
SYNC
SDI
SDO
RESET#
LINEOUT_L2+
LINEOUT_L2-
LINEOUT_R2+
LINEOUT_R2-
VL_HD
LINEIN_L+
LINEIN_C-
33
0.1 µF
Left Headphone
Headphone Ground
33
0.1 µF
Right Headphone
Differential to ‡
Single-Ended
Output Filter
+Left Line Output 1
Differential to ‡
Single-Ended
Output Filter
+Right Line Output 1
Differential to ‡
Single-Ended
Output Filter
+Left Line Output 2
Differential to ‡
Single-Ended
Output Filter
+Right Line Output 2
* Capacitors must be C0G or equivalent
1 µF
*
1800 pF
1 µF
Left Analog Input
+3.3 V
0.1 µF
VL_IF
LINEIN_R+
1 µF
*
1800 pF
Right Analog Input
GPIO2
GPIO3
*** SENSE_A
S/PDIF RX
S/PDIF TX 1
D-Mic In 2 / S/PDIF TX 2
D-Mic In 1
D-Mic Clk
*** See Figure 9.
GPIO2
GPIO3
SENSE_A
SPDIF_IN
SPDIF_OUT1
DMIC_SDA2/
SPDIF_OUT2
MICIN_L-
MICIN_L+
1 µF
1 µF
MICBIAS
0.47 µF
MICIN_R+
1 µF
RL
RL
DMIC_SDA1
DMIC_SCL
MICIN_R-
VCOM
VREF+
AGND
HP_GND(Thermal Pad)
1 µF
1 µF
10 µF
Differential Mic Left
Microphone Bias
The value of RL is dictated by
the microphone cartridge.
Differential Mic Right
‡ Input and Output
filters are optional.
Figure 1. Typical Connection Diagram - Desktop System
DS880F4
11

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