|
|
PDF HY5DU28422T Data sheet ( Hoja de datos )
| Número de pieza | HY5DU28422T | |
| Descripción | 2nd 128M DDR SDRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HY5DU28422T (archivo pdf) en la parte inferior de esta página. Total 57 Páginas | ||
|
No Preview Available !
HY5DU28422T
HY5DU28822T
HY5DU281622T
2nd 128M DDR SDRAM
HY5DU28422T
HY5DU28822T
HY5DU281622T
Revision 1.3
April 2001
Rev. 1.3 / Apr. 2001
This document is a general product description and is subject to change without notice.
1 page  
128Mb (x4, x8, x16) Double Data Rate SDRAM
HY5DU28422T
HY5DU28822T
HY5DU281622T
PIN DESCRIPTION
PIN
CK, /CK
CKE
/CS
BA0, BA1
A0 ~ A11
/RAS, /CAS, /WE
DM
(LDM,UDM)
DQS
(LDQS,UDQS)
DQ
VDD/VSS
VDDQ/VSSQ
VREF
NC
TYPE
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
Supply
Supply
Supply
NC
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corre-
sponds to the data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to the
data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
Data input / output pin : Data bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
Rev. 1.3 / Apr. 2001
5
5 Page 
128Mb (x4, x8, x16) Double Data Rate SDRAM
HY5DU28422T
HY5DU28822T
HY5DU281622T
WRITE MASK TRUTH TABLE
Function
Data Write
Data-In Mask
CKEn-1 CKEn CS, RAS, CAS, WE
HX
HX
X
X
DM
ADDR
A10/
AP
LX
HX
BA Note
1
1
Note :
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related
with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15)
respectively.
Rev. 1.3 / Apr. 2001
11
11 Page | ||
| Páginas | Total 57 Páginas | |
| PDF Descargar | [ Datasheet HY5DU28422T.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HY5DU28422AT | (HY5DU28xxxAT) 3rd 128M DDR SDRAM | Hynix Semiconductor |
| HY5DU28422DT | (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM | Hynix Semiconductor |
| HY5DU28422LT | (HY5DU28xxxAT) 3rd 128M DDR SDRAM | Hynix Semiconductor |
| HY5DU28422LT | (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM | Hynix Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |