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PDF LMX2314 Data sheet ( Hoja de datos )
| Número de pieza | LMX2314 | |
| Descripción | 1.2 GHz Frequency Synthesizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 1995
LMX2314 LMX2315 PLLatinumTM
1 2 GHz Frequency Synthesizer
for RF Personal Communications
General Description
The LMX2314 and the LMX2315 are high performance fre-
quency synthesizers with integrated prescalers designed for
RF operation up to 1 2 GHz They are fabricated using Na-
tional’s ABiC IV BiCMOS process
The LMX2314 and the LMX2315 contain dual modulus pre-
scalers which can select either a 64 65 or a 128 129 divide
ratio at input frequencies of up to 1 2 GHz Using a proprie-
tary digital phase locked loop technique the LMX2314 15’s
linear phase detector characteristics can generate very sta-
ble low noise local oscillator signals
Serial data is transferred into the LMX2314 and the
LMX2315 via a three line MICROWIRETM interface (Data
Enable Clock) Supply voltage can range from 2 7V to 5 5V
The LMX2314 and the LMX2315 feature very low current
consumption typically 6 mA at 3V
The LMX2314 is available in a JEDEC 16-pin surface mount
plastic package The LMX2315 is available in a TSSOP
20-pin surface mount plastic package
Features
Y RF operation up to 1 2 GHz
Y 2 7V to 5 5V operation
Y Low current consumption
ICC e 6 mA (typ) at VCC e 3V
Y Dual modulus prescaler 64 65 or 128 129
Y Internal balanced low leakage charge pump
Y Power down feature for sleep mode
ICC e 30 mA (typ) at VCC e 3V
Y Small-outline plastic surface mount JEDEC 0 150
wide (2314) or TSSOP 0 173 wide (2315) package
Applications
Y Cellular telephone systems
(GSM IS-54 IS-95 RCR-27)
Y Portable wireless communications
(DECT ISM902-928 CT-2)
Y Other wireless communication systems
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL W 11766
TL W 11766 – 1
RRD-B30M115 Printed in U S A
1 page  
Electrical Characteristics VCC e 5 0V VP e 5 0V b40 C k TA k 85 C except as specified (Continued)
Symbol
Parameter
Conditions
Min Typ Max Units
IDo-source
IDo-sink
IDo-Tri
Charge Pump Output Current
Charge Pump TRI-STATE Current
VDo e VP 2
VDo e VP 2
0 5V s VDo s VP b 0 5V
T e 85 C
b2 5
b5 0
50
25
mA
mA
nA
IDo vs VDo
Charge Pump Output Current
Magnitude Variation vs Voltage
(Note 1)
0 5V s VDo s VP b 0 5V
T e 25 C
15 %
IDo-sink vs
IDo-source
Charge Pump Output Current
Sink vs Source Mismatch
(Note 2)
VDo e VP 2
T e 25 C
10 %
IDovs T
Charge Pump Output Current
Magnitude Variation vs Temperature
(Note 3)
b40 C k T k 85 C
VDo e VP 2
10 %
VOH
VOL
VOH
VOL
IOL
IOH
RON
tCS
tCH
tCWH
tCWL
tES
tEW
High-Level Output Voltage
Low-Level Output Voltage
High-Level Output Voltage (OSCOUT)
Low-Level Output Voltage (OSCOUT)
Open Drain Output Current (wp)
IOH e b1 0 mA
IOL e 1 0 mA
IOH e b200 mA
IOL e 200 mA
VCC e 5 0V VOL e 0 4V
VCC b 0 8
VCC b 0 8
10
V
04 V
V
04 V
mA
Open Drain Output Current (wp)
VOH e 5 5V
100 mA
Analog Switch ON Resistance (2315)
100 X
Data to Clock Set Up Time
See Data Input Timing
50
ns
Data to Clock Hold Time
See Data Input Timing
10
ns
Clock Pulse Width High
See Data Input Timing
50
ns
Clock Pulse Width Low
See Data Input Timing
50
ns
Clock to Enable Set Up Time
See Data Input Timing
50
ns
Enable Pulse Width
See Data Input Timing
50
ns
Except OSCOUT
Notes 1 2 3 See related equations in Charge Pump Current Specification Definitions
5
5 Page 
Functional Description (Continued)
SERIAL DATA INPUT TIMING
TL W 11766 – 8
Notes Parenthesis data indicates programmable reference divider data
Data shifted into register on clock rising edge
Data is shifted in MSB first
Test Conditions The Serial Data Input Timing is tested using a symmetrical waveform around VCC 2 The test waveform has an edge rate of 0 6 V ns with
amplitudes of 2 2V VCC e 2 7V and 2 6V VCC e 5 5V
Phase Characteristics
In normal operation the FC pin is used to reverse the polari-
ty of the phase detector Both the internal and any external
charge pump are affected
Depending upon VCO characteristics FC pin should be set
accordingly
When VCO characteristics are like (1) FC should be set
HIGH or OPEN CIRCUIT
When VCO characteristics are like (2) FC should be set
LOW
When FC is set HIGH or OPEN CIRCUIT the monitor pin of
the phase comparator input fout is set to the reference
divider output fr When FC is set LOW fout is set to the
programmable divider output fp
VCO Characteristics
TL W 11766 – 9
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
Notes Phase difference detection range b2q to a2q
The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked
FC e HIGH
11
TL W 11766 – 10
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LMX2314.PDF ] | |
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