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PDF MC6808 Data sheet ( Hoja de datos )
| Número de pieza | MC6808 | |
| Descripción | Microprocessor | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC6808 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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MC6802
MC6808
MC6802NS
MICROPROCESSOR WITH CLOCK AND OPTIONAL RAM
The MC6802 is a monolithic 8-bit microprocessor that contains all the
registers and accumulators of the present MC~OO plus an internal clock
oscillator and driver on the same chip. In addition, the MCW02 has 128
bytes of on-board RAM located at hex addresses $~ to $O07F. The
first 32 bytes of RAM, at hex addresses $~ to $001 F, may be retained
in a low power mode by utilizing VCC standby; thus, facilitating
memory ietention during a power-down situation.
The MC6802 is completely software compatible with the MC68W as
well as the entire M~W family of parts. Hence, the MC6802 is expand-
able to WK words.
The MC6802NS is identical to the MC6802 without standby RAM
feature. The MC6808 is identical to the MC6802 without on-board
RAM,
q On-Chip Clock Circuit
q 128x8 Bit On-Chip RAM
~>,,~
q 32 Bytes of RAM are Retainable
;.\!J$;~: ,~:
q Software-Compatible
with the MC68~
q Expandable to 64K Words
q Standard TTL-Compatible Inputs and Outputs
q 8-Bit Word Size
~\R,!. t
*$\i,
~....,,.W~,~.:..;;‘.,,$,,‘~.>$~~$!..,‘~\~iM.,
.*.:X l~,o,?,
.f+.1$,.>t~,*,,,,.$.t.,.,~.$
. 16-8it Memory Addressing
q Interrupt Capability
~:t<y:i
“..>
,,.,,),? ,.,..
.,,$. .$.\.,!..,\.\,
+$,;{,, ~.$. >&,
~y,,$,’\\,..,.:‘,.Js:..~$4i,.:>.,/....,~b~,$, >.>l,i,y.
.,,.,{+? ,, “
‘,{$;:,~?s.~:.$q~:,i$~
.,,. a:.,,3,,
,~,,i..>~.,.~’:,>\\.)~t.’
,,.,,a+, :>‘~.,.-’
?;:<, \%:>.~t ,~
~,,,,)~.$t~~;~,,.r>.,!..K.,,?t.,,c.,K.,,..,.,.*!,.,:‘.?J:.,.~,.f$~,J+:
ORD,,,&,,:$~Q,%~~.,*,~>,l.JjFOR MATION
Package Type
Freq&&nc$@fiz)
Temperature
Ceramic
,,{:.$:.:f~ls$
L Suffix
,“~“.~NA~.:J,,x“v$*:i?\ .O
>?:$.,>+~,l,;.?.~*\...*.:\,.<:‘‘‘,$.:‘;.$.:ik:?,,$$ -
*...l,...~. ,’..i!\,f::.:.;:.\.(:.>~%tai~.,“:\
>,;~~,~j~.~’~\,,~.J3t,]...,\.*i,1\.,.t.v:3,,;\,,iv,
1.0
1.0
1.5
1.5
1.5
2.0
2.0
Ooc to 70”C
– 40°C to 85°C
Ooc to 70”C
O“c to 70°c
O“c to 70”C
–40°C to 85°C
O“c to 70°c
Ooc to 700c
O“c to 70°c
~e~ti~
1.0 O“c to 700c
P Suffix
1.0 –40°C to 85°C
1.0 Ooc to 700c
1.0 Ooc to 700c
1.5 Ooc to 700c
1.5 –40°C to 85°C
1.5 O“c to 70°c
2.0 Ooc to 700c
2.0 O“c to 700c
Order Number
M C6802L
MCM02CL
MC6802NSL
M C6808L
M C68A02L
M C68A02CL
MC68A08L
MC68B02L
MC68B08L
MC6802P
MC6802CP
M C6802N SP
M C6808P
MC68A02P
M C68A02CP
M C68A08P
MC68B02P
MC68B08P
..,,..,.., t..>i
P SUFFIX
LASTIC PACKAGE
CASE 711
PIN ASSIGNMENT
Vss[ 1.
HALT[ 2
VR[ 3
FQ [ 4
VLIA[ 5
NMI[ 6
BA[ 7
Vcc[ 8
AO [ 9
Al [ 10
A2 [ 11
A3 ~ 12
A4 [ 13
A5 [ 14
A6 [ 15
A7 [ 16
A8 [ 1?
A9 [ 18
A1O[ 19
40 )fl EsET
39 ]EXTAL
38 ] XTAL
37 ]E
36 ] RE**
35 ] VCC Standby*
34 J R/~
33 ] DO
32 ]Dl
31 ]D2
30 ] D3
29 ] D4
28 ] D5
27 ] D6
26 ] D7
25 ]A15
24 ]A14
23 ]A13
22 ]A12
* pin 35 mUSt be tied to 5 V on the MC6802NS
* * pin 36 must be tied to ground for the Mc6808
@MOTOROLA lNc , 1984
DS9818-R3
1 page  
FIGURE 3 – BUS TIMING TEST LOAD
4.75 v
?
C= 130 pF for DO-D7, E
=W pF for AO-A15, R/~, and VMA
=30 pF for BA
R= 11.7 k~ for DO-D7, E
= 16.5 kQ for AO-A15, R/~, and VMA
=24 kQ for BA
FIGURE 4 – TYPICAL DATA BUS OUTPUT DELAY
versus CAPACITIVE LOADING
600 I I I
- lo H=-205@[email protected]
lo L=l,[email protected]
500 -VCC=50V
- TA = 25°C
I
~ 400
5
u
z
G 300
>
a
d
0 200
/
100
CL fncludesstrav capacitance
o
0 100 200 300 400 500 600
CL, LOAD CAPACITANCE (PF)
..::\ .
FIGURE 6 – EXPANd%@:~*OCK DIAGRAM
A15 A14 A13 A12 All AlQ,.+ A~w’ A8
25 24 23 22 2SX 19“’” 18 17
A7 A6 A5 A4 A3 A2 Al
AO
16 15 14 13 12 11 10 9
I
Li
: m36 ‘AMEnab’e
I : =A35
‘Ccstandb,
VCC= Pin 8
Vcc= Pin 35 for MCW02NS
VSS=Pins
1, 21
VSS= P\n 36 for MC~08
Instruction
Register
I
m~ m
26 27 28 29 30 31 32 33
D? D6 D5 D4 D3 D2 DI DO
MOTOROLA
Semiconductor Products Inc.
5
5 Page 
FIGURE14–
MEMORY
READY
SYNCHRONIZATION
r4xfo
Oscillator
uI
The tpcs setup time is
E will be stretched in in-
The E clock will resume normal operation at the end of the fi cycle during which MR assertion meets the tpcs setup time, The tpcs setup time
is referenced to transitions of E were it not stretched. If tpcs setup time is not met, E will fail at the second possible transition time after MR is
asserted. There is no direct means of determining when the tpcs references occur, unless the svnchron!zing circuit of Figure 14 is used.
MOTOROLA
@
Semiconductor Products Inc.
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MC6808.PDF ] | |
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