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PDF MAX809 Data sheet ( Hoja de datos )
| Número de pieza | MAX809 | |
| Descripción | Very Low Supply Current 3-Pin Microprocessor Reset Monitors | |
| Fabricantes | ON Semiconducto | |
| Logotipo |  |
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1. MAX809 datasheet  Hay una vista previa y un enlace de descarga de MAX809 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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MAX809 Series,
MAX810 Series
Very Low Supply Current
3-Pin Microprocessor
Reset Monitors
The MAX809 and MAX810 are cost–effective system supervisor
circuits designed to monitor VCC in digital systems and provide a reset
signal to the host processor when necessary. No external components
are required.
The reset output is driven active within 10 µsec of V CC falling
through the reset voltage threshold. Reset is maintained active for a
minimum of 140 msec after V CC rises above the reset threshold. The
MAX810 has an active–high RESET output while the MAX809 has
an active–low RESET output. The output of the MAX809 is
guaranteed valid down to VCC = 1.0 V. Both devices are available in a
SOT–23 package.
The MAX809/810 are optimized to reject fast transient glitches on
the VCC line. Low supply current of 1.0 µA (VCC = 3.2 V) makes these
devices suitable for battery powered applications.
Features
• Precision VCC Monitor for 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies
• Precision Monitoring Voltages from 1.6 V to 4.9 V Available
in 100 mV Steps
• 140 msec Guaranteed Minimum RESET Output Duration
• RESET Output Guaranteed to VCC = 1.0 V
• Low Supply Current
• VCC Transient Immunity
• Small SOT–23 Package
• No External Components
• Wide Operating Temperature: –40°C to 105°C
Typical Applications
• Computers
• Embedded Systems
• Battery Powered Equipment
• Critical µP Power Supply Monitoring
VCC
VCC
MAX809/810
RESET
RESET
GND
VCC
PROCESSOR
RESET
INPUT
GND
Figure 1. Typical Application Diagram
© Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 4
1
http://onsemi.com
3
1
2
SOT–23
(TO–236)
CASE 318
See specific device marking
information on page 8.
MARKING
DIAGRAMS
3
xxxm
12
3
xxyw
12
xx, xxx = Specific Device Code
m = Date Code
y = Year
w = Work Week
PIN CONFIGURATION
GND 1
3 VCC
RESET** 2
(RESET)***
SOT–23*
(Top View)
NOTE: * SOT–23 is equivalent to JEDEC (TO–236)
** RESET is for MAX809
*** RESET is for MAX810
ORDERING INFORMATION
Device
Package
Shipping
MAX809xTR
SOT–23 3000 Tape/Reel
MAX809SNxxxT1 SOT–23 3000 Tape/Reel
MAX810xTR
SOT–23 3000 Tape/Reel
NOTE: The “x” and “xxx” denotes a suffix for Vcc voltage
threshold options – see page 8 for more details.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 8 of this data sheet.
Publication Order Number:
MAX809S/D
http://www.Datasheet4U.com
1 page  
MAX809 Series, MAX810 Series
APPLICATIONS INFORMATION
VCC Transient Rejection
The MAX809 provides accurate VCC monitoring and reset
timing during power–up, power–down, and brownout/sag
conditions, and rejects negative–going transients (glitches)
on the power supply line. Figure 2 shows the maximum
transient duration vs. maximum negative excursion
(overdrive) for glitch rejection. Any combination of
duration and overdrive which lies under the curve will not
generate a reset signal. Combinations above the curve are
detected as a brownout or power–down. Typically, transient
that goes 100 mV below the reset threshold and lasts 5µs or
less will not cause a reset pulse. Transient immunity can be
improved by adding a capacitor in close proximity to the CVC
pin of the MAX809.
VCC
VTH
Overdrive
Duration
120
100
80
60 VTH = 4.9 V
40
VTH = 1.6 V
20
0
10.0
60.0
110.0
160.0
RESET COMPARATOR OVERDRIVE (mV)
Figure 2. Maximum Transient Duration vs. Overdrive
for Glitch Rejection at 25°C
RESET Signal Integrity During Power–Down
The MAX809 RESET output is valid to V CC = 1.0 V.
Below this voltage the output becomes an “open circuit” and
does not sink current. This means CMOS logic inputs to the
µP will be floating at an undetermined voltage. Most digital
systems are completely shutdown well above this voltage.
However, in situations where RESET must be maintained
valid to VCC = 0 V, a pull–down resistor must be connected
from RESET to ground to discharge stray capacitances and
hold the output low (Figure 3). This resistor value, though
not critical, should be chosen such that it does not
appreciably load RESET under normal operation (100 kW
will be suitable for most applications).
VCC
VCC
MAX809/810
RESET
RESET
GND
R1
100 k
Figure 3. Ensuring RESET Valid to VCC = 0 V
Processors With Bidirectional I/O Pins
Some µP’s (such as Motorola 68HC1
1) have
bi–directional reset pins. Depending on the current drive
capability of the processor pin, an indeterminate logic level
may result if there is a logic conflict. This can be avoided by
adding a 4.7 k W resistor in series with the output of the
MAX809 (Figure 4). If there are other components in the
system which require a resetsignal, they should be bufered
so as not to load the reset line. If the other components are
required to follow the reset I/O of the µP, the buffer should
be connected as shown with the solid line.
VCC
VCC
MAX809/810
RESET
RESET
GND
4.7 k
BUFFER
BUFFERED RESET
TO OTHER SYSTEM
COMPONENTS
VCC
mP
RESET
GND
Figure 4. Interfacing to Bidirectional Reset I/O
http://onsemi.com
5
5 Page 
Notes
MAX809 Series, MAX810 Series
http://onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX809.PDF ] | |
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