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PDF MP2007 Data sheet ( Hoja de datos )

Número de pieza MP2007
Descripción DDR Memory Termination Regulator
Fabricantes MPS 
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No Preview Available ! MP2007 Hoja de datos, Descripción, Manual

MP2007
The Future of Analog IC Technology
3A, 1.3V–6.0V
DDR Memory Termination Regulator
DESCRIPTION
The MP20 07 integrates the DDR
memory
termination regulator with the ou tput voltage
(VTT) and a buffered VTTREF outp uts is a half
of VREF.
The VTT-LDO is a 3A sink/so urce tracking
termination regulator. It is spe cifically designed
for low-cost/low-external component count
systems, where space is a premium.
The MP20 07 maintains a fast
transient
response o nly requiring 20uF (2 x10uF) of
ceramic output capa citance. T he MP200 7
supports Kelvin sensing functions.
The MP2007 is available in the 8-pin MSOP with
Exposed PAD package and is specified from
40oC to 85oC.
FEATURES
VDDQ Voltage Range: 1.3V to 6.0 V
Up to 3A Integrated Sink/Source Linear
Regulator with Accur ate VREF/2 Divider
Reference for DDR Termination
Requires Only 20uF Ceramic Output
Capacitance
Drive Voltage Range: 4.5 V to 5.5 V
1.3V Input (VDDQ) Helps Reduce Total
Power Dissipation
Integrated Div ider Tracks VREF for VTT
and VTTREF
Kelvin Sensing (VTTSEN)
±20mV Accuracy for VTT and VTTREF
Built-In Soft-Start, UVLO and OCL
Thermal Shutdown
APPLICATIONS
Notebook DDR2/3 Memory Supply and
Termination Voltage in ACPI Compliant
Active Termination Busses
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VDDQ
R3
20
5V
EN
GND
R2
100k
C1
10uF
1
1206
6
DDQ
8
REF
VTTREF
C4
0.1uF MP2007DH
5
VDRV
C7
4.7uF
4
VTTSEN
7
VTTEN
GND
3
2
VTT
C2
10uF
1206
C6
0.1uF
C3
10uF
1206
C9
NC
VTTREF
GND
VTT
MP2007 Rev. 0.9
7/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
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MP2007 pdf
MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
TYPICAL PERFORMANCE CHARACTERISTICS
C1=C2=C3=10uF, C4 =C6=0.1uF, C7=4.7uF, VDRV=5V, TA=25ºC unless otherwise noted.
1 .3 7
1 .3 3
1 .2 9
1.25 VDDQ=2.5V
1 .2 1
VDDQ=1.8V
1 .1 7
-5 -4 -3 -2 -1 0 1 2 3 4 5
1. 02
0. 98
0. 94
0.9 VDDQ=2.5V
0.86 VDDQ=1.8V
0. 82
-5 -4 -3 -2 -1 0 1 2 3 4 5
0 .8 7
0 .8 3
0 .7 9
0.75 VDDQ=1.8V
0.71 VDDQ=1.5V
0 .6 7
-5 -4 -3 -2 -1 0 1 2 3 4 5
Source Load Transient
VDDQ=VREF=1.8V, V TT=0.9V
VTT
10mV/div.
ITT
1A/div.
20us/div
Sink Load Transient
VDDQ=VREF=2.5V, V TT=0.9V, VSINK=1.8V
Source Over Current Protection
VDDQ=VREF=2.5V, V TT=1.25V
VTT
10mV/div.
ITT
1A/div.
400us/div
VIN
2V/div.
VTTREF
1V/div.
VTT
1V/div.
ITT
2A/div.
400ms/div
Power Ramp Up
VDDQ=VREF=1.8V, V TT=0.9V
VDDQ
2V/div
VTTREF
2V/div.
VTT
0.5V/div.
ITT
1A/div.
4ms/div
Startup Through Down
VDDQ=VREF=1.8V, V TT=0.9V
Sink Over Current Protection
VDDQ=VREF=2.5V, V TT=1.25V,VSINK=2.5V
VDDQ
2V/div
VTTREF
2V/div.
VTT
0.5V/div.
ITT
1A/div.
10ms/div
VDDQ
2V/div
VTTREF
1V/div.
VTT
1V/div.
ITT
2A/div.
1s/div
MP2007 Rev. 0.9
7/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
5

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MP2007 arduino
MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
PACKAGE INFORMATION
0.114(2.90)
0.122(3.10)
85
MSOP8E (EXPOSED PAD)
0.087(2.20)
0.099(2.50)
PIN 1 ID
(NOTE 5)
0.114(2.90)
0.122(3.10)
0.187(4.75)
0.199(5.05)
0.062(1.58)
0.074(1.88)
0.010(0.25)
0.014(0.35)
1
4
0.0256(0.65)BSC
TOP VIEW
Exposed Pad
BOTTOM VIEW
0.030(0.75)
0.037(0.95)
FRONT VIEW
0.043(1.10)MAX
SEATING PLANE
0.002(0.05)
0.006(0.15)
GAUGE PLANE
0.010(0.25)
0o-6o
0.016(0.40)
0.026(0.65)
SIDE VIEW
0.004(0.10)
0.008(0.20)
0.075(1.90)
0.100(2.54)
0.040(1.00)
0.181(4.60)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS
IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) PIN 1 IDENTIFICATION HAS HALF OR FULL CIRCLE OPTION.
6) DRAWING MEETS JEDEC MO-187, VARIATION AA-T.
7) DRAWING IS NOT TO SCALE.
0.016(0.40)
0.0256(0.65)BSC
RECOMMENDED LAND PATTERN
NOTICE: The information in this docum ent is subject to chang e without notice. Users sh ould warrant and guarantee that third
party Int ellectual Prop erty r ights are n ot inf ringed u pon when i ntegrating MPS product s into any application. MPS w ill not
assume any legal responsibility for any said applications.
MP2007 Rev. 0.9
7/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
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