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PDF AK8136A Data sheet ( Hoja de datos )

Número de pieza AK8136A
Descripción Low Power Multiclock Generator
Fabricantes AKM 
Logotipo AKM Logotipo



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AK8136A
Low Power
Multiclock Generator with VCXO
AK8136A
Features
27MHz Crystal Input
One 27MHz-Reference Output
2 wire serial register interface
Selectable Clock out Frequencies:
- 148.352, 148.5MHz
- 100.71, 108MHz
- 22.5792, 24.576, 33.8688, 36.864MHz
- 27.0MHz
Built-in VCXO
- Pull Range: ±150ppm (typ.)
Low Jitter Performance
- Period Jitter:
150 psec (Typ.) at CLK2,CLK3,CLK4
- TIE
100 psec (Max) at CLK1p,CLK1n
- Long term jitter
160 psec (Typ.) at REFOUT
Low Current Consumption:
32 mA (Typ.) at 3.3V
Supply Voltage:
3.0 3.6V
Operating Temperature Range:
-20 to +85
Package:
20-pin SSOP (Lead free, Halogen free)
Description
The AK8136A is a member of AKMs low power
multi clock generator family designed for a feature
rich DTV or STB, requiring a range of system
clocks with high performance. The AK8136A
generates different frequency clocks from a 27MHz
crystal oscillator and provides them to up to four
outputs configured by register-setting. The on-chip
VCXO accepts a voltage control input to allow the
output clocks to vary by ±150 ppm for
synchronizing to the external clock system. Both
circuitries of VCXO and PLL in AK8136A are
derived from AKMs long-term-experienced clock
device technology, and enable clock output to
perform low jitter and to operate with very low
current consumption. The AK8136A is available
in a 20-pin SSOP package.
Applications
Set-Top-Boxes
VDD
XI
XO
VIN
Voltage
Controlled
Crystal
Oscillator
Full PD
SDA Control
SCL Register
PLL1
PLL2
PLL3
CLK1p
CLK1n
CLK2
CLK3
CLK4
REFOUT
VREF
MS1108-E-04
GND
AK8136A Multi Clock Generator
-1-
Dec-2013
http://www.Datasheet4U.com

1 page




AK8136A pdf
AK8136A
AC Characteristics (Clock signals)
VDD: over 3.0 to 3.6V, VDDI over 1.7 to 3.6V,Ta: over -20 to +85, 27MHz Crystal, unless otherwise noted
Parameter
Symbol
Conditions
MIN TYP MAX Unit
Crystal Clock Frequency
Output Clock Accuracy
VCXO Pullable Range (1)
Fosc
Faccuracy
PRvcxo
Pin:XI,XO
Pin:CLK2 100.71MHz
Relative to 27.0MHz
VIN at over 0 to VDD V
27.0000
106.25
±150
MHz
ppm
ppm
VCXO Gain
Period Jitter (5)
Time Interval Error (6)
Long Term Jitter (7)
Output Clock Duty
Cycle
Output Clock Slew Rate
Slew rate matching
Differential output swing
Crossing point voltage
Variation of Vcrs
Maximum output voltage
Minimum output voltage
Output Clock Rise Time
Output Clock Fall Time
Output enable/disable Time(8)
Power-up Time 1(9)
Power-up Time 2(10)
GVCXO
Jit_period
Jit_tie
Jit_long
DtyCyc
Slew_rise_fall
Slew_ver
V_swing
V_cross
V_cross_delta
V_max
V_min
T_rise
T_fall
T_en_dis
T_put1
T_put2
VIN range at 1.5V±1.0V
Pin:REFOUT(2),CLK2-4(3)
Pin:CLK1(4)
Pin:REFOUT
1000 cycle delay
Pin: CLK1p,n(4) Figure.3
CLK2-4 (3)
Pin: REFOUT (2)
Pin:CLK1p,n (4) Figure.3
Pin:CLK1p,n (4) Figure.2
Pin:CLK1p,n (4) Figure.3
Pin:CLK1p,n (4) Figure.2
Pin:CLK1p,n (4) Figure.2
Pin:CLK1p,n (4) Figure.2
Pin:CLK1p,n (4) Figure.2
Pin: CLK2-4 (3)
Pin: REFOUT (2 )
Pin: CLK2-4 (3)
Pin: REFOUT (2 )
Pin: REFOUT,CLK1p,n
CLK2-4
Pin: REFOUT,CLK1p,n
CLK2-4
Pin: REFOUT,CLK1p,n
CLK2-4
45
40
2.5
300
300
-0.3
150
150
(6σ)
160
50
50
1.0
2.5
1.0
2.5
ppm/V
ps
100 ps
ps
55 %
60 %
8.0 V/ns
20 %
mV
550 mV
140 mV
1.15 V
V
3.0 ns
5.0 ns
3.0 ns
5.0 ns
500 ns
4 ms
150 ms
(1) Pullable range depends on crystal characteristics, on-chip load capacitance, and stray capacity of PCB.
Typ. ±150ppm is applied to AKMs authorized test condition.
Please contact us when you plan the use of other crystal unit.
(2) Measured with load capacitance of 25pF
(3) Measured with load capacitance of 15pF
(4) Measured with load condition shown in Figure.1
(5) ±3in 10000 sampling or more
(6) 16ms accumulate with higher than 10GSa/s.
(7) ±3in 10000 sampling or more
(8) Refer to Figure.7 on Clock enable and disable sequence.
(9) Time to settle output into 0.1% of specified frequency from FULL_PD is L.
Power Down sequence.
(10) Refer to Figure.5 on Power on Reset sequence.
Refer to Figure.6 on Full
MS1108-E-04
-5-
Dec-2013

5 Page





AK8136A arduino
AK8136A
Random read
Random read operation is described below. It is necessary to operate dummy writebefore sending
read command. Dummy write is to send the address to read.
Random read
SDA 1 0 1 0 1 1 0 0
S Device Device R A
T Address Address / C
A
R
-1
-2 W K
T
Dummy Write
Address
(MSB First)
10101101
AS
CT
KA
R
T
Device
Address
-1
Device R A
Address / C
-2 W K
Data
(MSB First)
NS
OT
A
C
O
P
K
Sequential read
Sequential read operation is described below. It is possible to read next address sequentially by
sending ACK instead of stop condition.
Sequential read
SDA ・・・・ 1 1 0 1
・・・・
Device R A Data (MSB First) A Data (MSB First) A
Address / C
-2 W K
(Address)
C
K
(Address+1)
C
K
A Data (MSB First) N S
C
K
(Address+n)
OT
A
C
O
P
K
Change data
Change data operation is described below. It is available when SCL is Low.
Change data
SCL
SDA
DATA STABLE
DATA
CHANGE
Start / Stop timing
Start / Stop timing is described below. The sequence is started when SDA goes from high to low
during SCL is high. The sequence is stopped when SDA goes from low to high during SCL is high.
Start / Stop timing
SCL
SDA
START
STOP
MS1108-E-04
- 11 -
Dec-2013

11 Page







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