DataSheet.es    


PDF AK7601A Data sheet ( Hoja de datos )

Número de pieza AK7601A
Descripción High Feature Digital Audio Processor
Fabricantes AKM 
Logotipo AKM Logotipo



Hay una vista previa y un enlace de descarga de AK7601A (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! AK7601A Hoja de datos, Descripción, Manual

[AK7601A]
AK7601A
High Feature Digital Audio Processor with SRC
GENERAL DESCRIPTION
AK7601A is a high feature audio processor with audio CODEC (3ch ADC, 6ch DAC) and delay line
memory operates 5.0V single power supply. The analog inputs support quasi-differential/single-ended
with 4:1 stereo selector in front of 2-channeled 97dB ADC, and monaural ADC for guidance sound. The
digital inputs supports 3:1 input selector with asynchronous Sample Rate Converter (SRC) for digital
source such as DVD, Blu-ray, digital broadcasting, etc. The high performance 6-channeled DAC
integrates full-range digital volume control and achieves 102dB with single end outputs. The delay line
memory covers 36ms in total. Time alignment of 6m or less is possible since the delay line memory can
store for 18ms data for both left and right channels. The AK7601A can achieve high performance car
audio system easily by supporting two stereo 7-band EQ and time alignment functions.
FEATURES
1. 2ch 24bit ADC
- Quasi-Differential/Single-ended inputs with 4:1 Stereo Selector
- S/(N+D): 90dB
- DR, S/N: 97dB
- Digital HPF for cancelling DC offset
2. 1ch 24bit ADC for Monaural Audio Input
- Single-ended input
- S/(N+D): 90dB
- DR, S/N: 97dB
- Digital HPF for cancelling DC offset
3. 6ch 24bit DAC
- Single-ended output
- S/(N+D): 90dB
- DR, S/N: 102dB
4. Asynchronous Sample Rate Converter(SRC) for Digital Input
- 3:1 Input Selector
- Input Sampling Rate: 8kHz 96kHz
- Data Format: MSB justified, LSB justified, I2S compatible (slave mode only)
5. Digital Processing
- Two Stereo 7Band EQ (Second-order IIR-filter setting is also available)
- Digital De-emphasis Filter
- Adjustable Delay Memory Control
Maximum Delay Time:
Lch 18ms, Rch 18ms (for 1 stereo input / 3 stereo outputs)
Delay Resolution: 1/fs
- X’Over filter:
Front L, Front R: 2nd order IIR Filter x 3 stages
Rear L, Rear R, Subwoofer L, Subwoofer R: 2nd order IIR Filter x 2 stages
- Spectrum analyzer: Variable 4-Band
- Soft Mute
- Zero Detect Function
6. Smooth Volume
7. Master Clock
- Master Mode: 22.5792MHz
8. μP Interface: I2C Bus (Ver 1.0, 400kHz mode)
MS1446-E-00
-
1-
2012/07
http://www.Datasheet4U.com

1 page




AK7601A pdf
Note 1. All digital input pins must not be allowed to float.
Note 2. Input pin when powered-down.
Note 3. Output pin when powered-down
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below
Classification Pi
Analog
Digital
n Name
AINL1, GNDIN1, AINR1, AINL2, GNDIN2, AINR2,
AINL3, AINR3, AINL4, AINR4, MONOIN
AOUT1L, AOUT1R, AOUT2L, AOUT2R, AOUT3L,
AOUT3R
IBICK1, IB ICK2, IBICK3, ILRC K1, ILRC K2,
ILRCK3, SDTI1, SDTI2, SDTI3, SDTI4
OBICK, OLRCK, MCKO, SDTO1/SDTO3, SDTO2,
XTO
Setting
Open
Open
Connect to VSS2
Open
[AK7601A]
MS1446-E-00
-
5-
2012/07

5 Page





AK7601A arduino
[AK7601A]
SWITCHING CHARACTERISTICS
(Ta=-40+85°C; AVDD=4.5~5.5V; DVDD=3.05.5V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
--
-
22.5792
-
MHz
MCKO Output
Frequency MCKO1-0 bit = “10”
fMCK
-
22.5792
-
MHz
MCKO1-0 bit = “01”
fMCK
-
11.2896
-
MHz
Duty cycle 512fs (Note 17)
dMCK
40
50 60 %
256fs (Note 17)
dMCK
45
50 55 %
External Clock
Frequency
fCLK
22.35
22.5792 22.80
MHz
Pulse Width Low
tCLKL
18
ns
Pulse Width High
tCLKH
18
ns
MCKO Output
Frequency 512fs
fMCK
22.35
22.5792 22.80
MHz
Duty cycle (Note 18)
dMCK
40
50 60 %
Input LRCK (ILRCK1-3)
Frequency
FSI 8
96 kHz
Duty Cycle
Duty 48 50 52 %
Output LRCK (OLRCK)
Frequency
FSO - 44.1 - kHz
Duty Cycle
Duty
50 %
Audio Interface Timing
OBICK Frequency
OBICK Duty
OBICK “” to OLRCK
OBICK “” to SDTO1~3
SDTI3-4 Hold Time
SDTI3-4 Setup Time
Input PORT
IBICK1-3 Period
IBICK1-3 Pulse Width Low
Pulse Width High
ILRCK1-3 Edge to IBICK1-3 “” (Note 19)
IBICK1-3 “” to ILRCK1-3 Edge (Note 19)
SDTI1-3 Hold Time from IBICK1-3 “
SDTI1-3 Setup Time to IBICK1-3 “
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDL
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
-
-
20
20
30
30
1/64fs
65
65
30
30
30
30
64fs
50
-
-
-
-
20
20
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 17. According to the crystal oscillator values in Table 2.
Note 18. In the case of MCKO1-0bits = “10” (22.5792MHz), these are the values when External Clock Duty is 50%.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
MS1446-E-00
-
11 -
2012/07

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet AK7601A.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
AK7601AHigh Feature Digital Audio ProcessorAKM
AKM

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar