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PDF APL3216 Data sheet ( Hoja de datos )
| Número de pieza | APL3216 | |
| Descripción | Li+ Charger Protection IC | |
| Fabricantes | ANPEC | |
| Logotipo |  |
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APL3216
Li+ Charger Protection IC
Features
• Provide Input Over-voltage Protection
• Provide Input Over-current Protection
• Provide Over Temperature Protection
• Provide Reverse Current Blocking
• High Immunity of False Triggering
• High Accuracy Protection Threshold
• Low On Resistance 0.75Ω Typ.
• Compliance to IEC61000-4-2 (Level 4)
+8kV (Contact Discharge)
+15kV (Air Discharge)
• Available in TDFN2x2-8, SOT-23-6 Packages
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
• Cell Phones
Simplified Application Circuit
5V Adapter
ACIN CHR_LDO
APL3216
GATDRV
VCDT
OUT
GND
CHR_LDO
PMIC
GATDRV
VCDT
ISENS
Li+
Battery
VBAT
General Description
The APL3216 provides complete Li+ charger protection
against Input over-voltage, input over-current and over-
temperature. When any of the monitored parameters is
over the threshold, the IC turns off the charging current.
All protections also have deglitch time against false trig-
gering due to voltage spikes or current transients.
When ACIN voltage exceeds OVP threshold, the device
will turn off charging current. The charging current is con-
trolled by the GATDRV pin. When sourcing a current from
the GATDRV pin, the OUT pin delivers the charging cur-
rent which is 200-fold magnified in amplitude based on
GATDRV’s current.
Other features include accurate VVCDT/VACIN Voltage divider,
reverse current blocking from OUT to ACIN and OTP
protection. The L3216 provides complete Li+ charger
protections, that can save the external components for
the charger of cell phone’s PMIC. The above features
and small package make the APL3216 an ideal part for
cell phones applications.
Pin Configuration
ACIN 1
ACIN 2
GND 3
VCDT 4
8 OUT
7 OUT
6 CHR_LDO
5 GATDRV
TDFN2x2-8
(Top View)
OUT 1
CHR_LDO 2
GATDRV 3
6 ACIN
5 GND
4 VCDT
SOT-23-6
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.7 - Dec., 2011
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
1 page  
APL3216
Typical Application Circuit
5V
Adapter
CACIN
1µF/25V
ACIN CHR_LDO
APL3216
GATDRV
VCDT
OUT
GND
CHR_LDO
CCHR_LDO
2.2µF/6.3V
PMIC
GATDRV
VCDT
ISENS
0.2Ω
Li+
Battery
VBAT
Designation
CACIN
CCHR_LDO
Description
1µF, 25V, X5R, 0603
Murata GRM188R61E105K
1µF, 16V, X5R, 0603
Murata GRM188R61C105K
1µF, 6.3V, X5R, 0603
Murata GRM185R60J225KE26
Copyright © ANPEC Electronics Corp.
Rev. A.7 - Dec., 2011
5
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
5 Page 
APL3216
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax)
3 °C/second max.
183 °C
60-150 seconds
See Classification Temp in table 1
20** seconds
6 °C/second max.
3°C/second max.
217 °C
60-150 seconds
See Classification Temp in table 2
30** seconds
6 °C/second max.
Time 25°C to peak temperature
6 minutes max.
8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Volume mm3
Thickness
<350
<2.5 mm
235 °C
≥2.5 mm
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Volume mm3
Thickness
<350
<1.6 mm
260 °C
1.6 mm – 2.5 mm
260 °C
≥2.5 mm
250 °C
Volume mm3
350-2000
260 °C
250 °C
245 °C
Volume mm3
≥350
220 °C
220 °C
Volume mm3
>2000
260 °C
245 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
ESD
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
JESD-22, A114; A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM 2KV, VMM 200V
10ms, 1tr 100mA
Copyright © ANPEC Electronics Corp.
Rev. A.7 - Dec., 2011
11
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet APL3216.PDF ] | |
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