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PDF RT7257E Data sheet ( Hoja de datos )
| Número de pieza | RT7257E | |
| Descripción | Synchronous Step-Down Converter | |
| Fabricantes | Richtek | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RT7257E (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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SacPower
Preliminary
RT7257E
3A, 17V, 340kHz Synchronous Step-Down Converter
General Description
The RT7257E is a high efficiency, monolithic synchronous
step-down DC/DC converter that can deliver up to 3A
output current from a 4.5V to 17V input supply. The
RT7257E's current mode architecture and external
compensation allow the transient response to be
optimized over a wide range of loads and output capacitors.
Cycle-by-cycle current limit provides protection against
shorted outputs, and soft-start eliminates input current
surge during start-up. The RT7257E provides thermal
shutdown protection. The low current (<3μA) shutdown
mode provides output disconnection, enabling easy power
management in battery-powered systems. The RT7257E
is available in an SOP-8 (Exposed Pad) package.
Ordering Information
RT7257EN
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
Features
z ±1.5% High Accuracy Feedback Voltage
z 4.5V to 17V Input Voltage Range
z 3A Output Current
z Integrated N-MOSFET Switches
z Current Mode Control
z Fixed Frequency Operation : 340kHz
z Output Adjustable from 0.8V to 15V
z Up to 95% Efficiency
z Programmable Soft-Start
z Stable with Low ESR Ceramic Output Capacitors
z Cycle-by-Cycle Over Current Protection
z Input Under Voltage Lockout
z Thermal Shutdown Protection
z RoHS Compliant and Halogen Free
Applications
z Wireless AP/Router
z Set-Top-Box
z Industrial and Commercial Low Power Systems
z LCD Monitors and TVs
z Green Electronics/Appliances
z Point of Load Regulation of High-Performance DSPs
Pin Configurations
(TOP VIEW)
BOOT
VIN
SW
GND
8
27
GND
36
9
45
SS
EN
COMP
FB
SOP-8 (Exposed Pad)
0755-83983280
1
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1 page  
Preliminary
RT7257E
Parameter
Symbol
EN Input Threshold
Voltage
Logic-High
Logic-Low
Input Under Voltage Lockout Threshold
Input Under Voltage Lockout Hysteresis
VIH
VIL
VUVLO
ΔVUVLO
Soft-Start Current
Soft-Start Period
Thermal Shutdown
ISS
tSS
TSD
Test Conditions
VIN Rising
VSS = 0V
CSS = 0.1μF
Min Typ Max Unit
2 -- 5.5
V
-- -- 0.4
3.8 4.2 4.5
V
-- 320 -- mV
-- 6 -- μA
-- 13.5 --
-- 150 --
ms
°C
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
5
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5 Page 
Preliminary
RT7257E
The output ripple will be the highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, VIN. At best, this
ringing can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part.
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on SW pin when
high side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One is to place an R-C
snubber between SW and GND and make them as close
as possible to the SW pin (see Figure 5). Another method
is adding a resistor in series with the bootstrap
capacitor, CBOOT. But this method will decrease the driving
capability to the high side MOSFET. It is strongly
recommended to reserve the R-C snubber during PCB
layout for EMI improvement. Moreover, reducing the SW
trace area and keeping the main power in a small loop will
be helpful on EMI performance. For detailed PCB layout
guide, please refer to the section of Layout Consideration.
VIN
4.5V to 17V
Chip Enable
REN*
CEN*
2 VIN
BOOT 1
CIN
10µF x 2
RT7257E
SW 3
7 EN
8 SS
CSS
4,
0.1µF 9 (Exposed Pad) GND
FB 5
COMP 6
RBOOT*
CBOOT L
100nF 10µH
RS*
CS*
CC
4.7nF
RC
12k
R1
75k
R2
24k
VOUT
3.3V/3A
COUT
22µFx2
* : Optional
CP
NC
Figure 5. Reference Circuit with Snubber and Enable Timing Control
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT7257E, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance θJA is 75°C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm2copper area PCB layout)
11
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11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet RT7257E.PDF ] | |
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