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PDF TRC105 Data sheet ( Hoja de datos )
| Número de pieza | TRC105 | |
| Descripción | RF Transceiver | |
| Fabricantes | RF Monolithics | |
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Product Overview
TRC105 is a single chip, multi-channel, low power UHF transceiver. It is
designed for low cost, high volume, two-way short range wireless applica-
tions in the 300 to 510 MHz frequency range. The TRC105 is FCC & ETSI
certifiable. All critical RF and base-band functions are integrated in the
TRC105, minimizing external component count and simplifying and speeding
design-ins. A microcontroller, RF SAW filter, 12.8 MHz crystal and a few pas-
sive components are all that is needed to create a complete, robust radio
function. The TRC105 incorporates a set of low-power states to reduce cur-
rent consumption and extend battery life. The small size and low power con-
sumption of the TRC105 make it ideal for a wide variety of short range radio
applications. The TRC105 complies with Directive 2002/95/EC (RoHS). Pb
TRC105
300-510 MHz
RF Transceiver
Key Features
Modulation: FSK or OOK with frequency hop-
ping spread spectrum capability
Frequency range: 300 to 510 MHz
High sensitivity: -112 dBm in circuit
High data rate: up to 200 kb/s
Low receiver current: 2.7 mA typical
Low sleep current: 0.1 µA typical
Up to +13 dBm in-circuit transmit power
Operating supply voltage: 2.1 to 3.6 V
Programmable preamble
Programmable packet start pattern
Integrated RF, PLL, IF and base-band circuitry
Integrated data & clock recovery
Programmable RF output power
PLL lock output
Transmit/receive FIFO size programmable up
to 64 bytes
Continuous, buffered and packet data modes
Packet address recognition
Packet handling features:
Fixed or variable packet length
Packet filtering
Packet formatting
Standard SPI interface
TTL/CMOS compatible I/O pins
Programmable clock output frequency
Low Battery Detection
Low cost 12.8 MHz crystal reference
Integrated RSSI
Integrated crystal oscillator
Host processor interrupt pins
Programmable data rate
External wake-up event inputs
Integrated packet CRC error detection
Integrated DC-balanced data scrambling
www.DataSheet.net/
Integrated Manchester encoding/decoding
Interrupt signal mapping function
Support for multiple channels
Four power-saving modes
Low external component count
TQFN-32 SMT package
Standard 13 inch reel, 3K pieces
Applications
Active RFID tags
Automated meter reading
Home & industrial automation
Security systems
Two-way remote keyless entry
Automobile immobilizers
Sports performance monitoring
Wireless toys
Medical equipment
Low power two-way telemetry systems
Wireless mesh sensor networks
Wireless modules
© 2009-2012 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 1 of 67
TRC105 - 10/16/12
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
2.0 Functional Description
The TRC105 is a single-chip transceiver that can operate in the 300-510 MHz frequency range. The TRC105
supports two modulation schemes - FSK and OOK. The TRC105’s highly integrated architecture requires a mini-
mum of external components, while maintaining design flexibility. All major RF communication parameters are
programmable and most can be dynamically set. The TRC105 is optimized for very low power consumption (2.7
mA typical in receiver mode). It complies with European ETSI, FCC Part 15 and Canadian RSS-210 regulatory
standards. Advanced digital features including the TX/RX FIFO and the packet handling data mode significantly
reduce the load on the host microcontroller.
T R C 1 0 5 B lo c k D ia g r a m
R F+
R F-
C LK O U T
T X L O 1 -I
OOK
M o d u la tio n
In p u t
P ow er
Am p
D r iv e r
+
-
+
T X L O 2 -I
T X L O 2 -Q
-
+
T X L O 2 -I
T X L O 2 -Q
+
A n ti-
a lia s in g
F ilte r
A n ti-
a lia s in g
F ilte r
DAC
T r a n s m it
W a v e fo rm
G e n e ra to r
DAC
T X L O 1 -Q
RSSI
R e c e iv e r
L N A B a n d -p a s s
F ilte r
VG A
R X LO 1
R X L O 2 -I
R -C
L o w -p a s s
F ilte r
B u tte rw o rth
or
P o ly p h a s e
F ilte r
IF A m p lifie r
L im ite r
R -C
L o w -p a s s
F ilte r
B u tte rw o rth
or
P o ly p h a s e
F ilte r
www.DataSheet.net/
IF A m p lifie r
L im ite r
OOK
D e te c to r
FSK
D e te c to r
D a ta &
C lo c k
R e c o v e ry
C o n tro l
SCK
SDI
SDO
nS S _D A TA
n S S _ C O N F IG
D A TA
IR Q 1 /D C L K
IR Q 0
P LL_LO C K
R X L O 2 -Q
O s c illa to r
D iv id e r &
B u ffe r
C ry s ta l
O s c illa to r
VCO
F re q u e n c y
D iv id e r
R e fe re n c e
F re q u e n c y
D iv id e r
P hase
D e te c to r
C h a rg e
Pum p
PLL
Loop
F ilte r
VCO
D iv id e
by 8
D iv id e
by 8
I& Q
P hase
T X L O 2 -I
T X L O 2 -Q
T X L O 1 -I
T X L O 1 -Q
R X LO 1
R X L O 2 -I
R X L O 2 -Q
F IF O
Figure 1
The receiver is based on a superheterodyne architecture. It is composed of the following major blocks:
An LNA that provides low noise RF gain followed by an RF band-pass filter.
A first mixer which down-converts the RF signal to an intermediate frequency equal to 1/9th of the carrier
frequency.
A variable gain first IF preamplifier followed by two second mixers which down convert the first IF signal to
I and Q signals at a low frequency (zero-IF for FSK, low-IF for OOK).
© 2009-2012 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 5 of 67
TRC105 - 10/16/12
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
2.6 PLL Loop Filter
The loop filter for the frequency synthesizer is shown in Figure 6.
PLL Loop Filter
Figure 6
PLL Loop Filter Components
Name
C8
C9
R1
Value
1000 pF
6800 pF
6.8 kΩ
Tolerance
±10%
±10%
±5%
Table 6
Recommended component values for the frequency synthesizer loop filter are provided in Table 6. The loop filter
settings are not dependent on the frequency band, so they can be used on all designs. PLL lock status can be
provided on Pin 23 by setting the IRQCFG0E_PLL_LOCK_EN[0] bit to a 1. Pin 23 goes high when the PLL is
locked. The lock status of the PLL can also be checked by reading the IRQCFG0E_PLL_ LOCK_ST[1] bit. This
bit latches high each time the PLL locks and must be reset by writing a 1 to it.
3.0 Operating Modes
The TRC105 has 5 possible chip-level modes. The chip-level mode is set by MCFG00_Chip_Mode[7..5], which
is a 3-bit pattern in the configuration register. Table 7 summarizes the chip-level modes:
MCFG00_Chip_Mode[7..5]
000
001
010
011
100
Chip-level Mode Enabled Functions
Sleep
None
Standby
Crystal oscillatorwww.DataSheet.net/
Synthesizer
Crystal and frequency synthesizer
Receive
Crystal, frequency synthesizer and receiver
Transmit
Crystal, frequency synthesizer and transmitter
Table 7
Table 8 gives the state of the digital pins for the different chip-level modes and settings:
PIN Function
nSS_CONFIG*
nSS_DATA*
IRQ0
IRQ1
DATA
CLKOUT
SDO**
SDI
SCK
Sleep
Mode
I
I
TRI
TRI
TRI
TRI
TRI/O
I
I
Standby
Mode
I
I
O
O
TRI
O
TRI/O
I
I
Synthesizer
Mode
I
I
O
O
TRI
O
TRI/O
I
I
Receive
Mode
I
I
O
O
O
O
TRI/O
I
I
I = Input, O = Output, TRI = High Impedance
*nSS_CONFIG has priority OVER nSS_DATA
**SDO is an output if nSS CONFIG = 0 and/or nSS DATA = 0
Table 8
Transmit
Mode
I
I
O
O
I
O
TRI/O
I
I
© 2009-2012 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 11 of 67
TRC105 - 10/16/12
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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| PDF Descargar | [ Datasheet TRC105.PDF ] | |
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