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PDF AD9739 Data sheet ( Hoja de datos )
| Número de pieza | AD9739 | |
| Descripción | RF Digital-to-Analog Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9739 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Data Sheet
FEATURES
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix mode
Industry leading single/multicarrier IF or RF synthesis
fOUT = 350 MHz, ACLR =80 dBc
fOUT = 950 MHz, ACLR = 78 dBc
fOUT = 2100 MHz, ACLR = 69 dBc
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin-compatible with the AD9739A
Multichip synchronization capability
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.16 W at 2.5 GSPS
APPLICATIONS
Broadband communications systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9739 is a 14-bit, 2.5 GSPS high performance RF digital-
to-analog converter (DAC) capable of synthesizing wideband
signals from dc up to 3.0 GHz. Its DAC core features a quad-
switch architecture that provides exceptionally low distortion
performance with an industry-leading direct RF synthesis
capability. This feature enables multicarrier generation up to
the Nyquist frequency in baseband mode as well as second and
third Nyquist zones in mix mode. The output current can be
programmed over the 8.66 mA to 31.66 mA range.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. Multichip synchronization is possible
with an on-chip synchronization controller. A serial peripheral
interface (SPI) is used for device configuration as well as readback
of status registers.
The AD9739 is manufactured on a 0.18 μm CMOS process and
operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball
chip scale ball grid array for reduced package parasitics.
14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converter
AD9739
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
SDIO
SDO
CS
SCLK
AD9739
1.2V
SPI DAC BIAS
VREF
I120
IOUTP
DCI
TxDAC
CORE
IOUTN
DCO
SYNC_OUT
SYNC_IN
CLK DISTRIBUTION
(DIV-BY-4)
SYNC-
CONTROLLER
Figure 1.
DACCLK
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix
mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
5. A multichip synchronization capability.
6. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9739
Manually Section, and Calculating Mu Delay Line Step Size
Section.............................................................................................. 42
Added Output Stage Configuration Section and Figure 66 to
Figure 70 .......................................................................................... 42
Added Nonideal Spectral Artifacts Section, Figure 71, and
Table 30 ............................................................................................ 43
Deleted Operation in Master Mode, Figure 93, and Figure 94 .......44
Added Lab Evaluation of the AD9739 Section, Power Dissipation
and Supply Domains Section, and Figure 72 to Figure 74 ........ 44
Deleted Figure 95, Operation in Slave Mode Section, and Data
Receiver Operation in Auto Mode Section ................................. 45
Changes to Recommended Start-Up Sequence Section............ 45
Added Figure 75.............................................................................. 45
Deleted Figure 97, Data Receiver Operation in Manual Mode
Section, Calculating the DCI Delay Line Step Size Section, and
Maximum Allowable Data Timing Skew/Jitter Section ............ 46
Added Table 31 ............................................................................... 46
Data Sheet
Deleted Optimizing the Clock Common-Mode Voltage Section,
Figure 99, Analog Control Registers Section, Mirror Roll-Off
Frequency Control Section, and Figure 101 ............................... 47
Added Table 32 ............................................................................... 47
Deleted Figure 103, Figure 104, and Figure 106......................... 48
Updated Outline Dimensions....................................................... 48
Deleted Figure 107 to Figure 109 ................................................. 49
Deleted Table 35 to Table 44 ......................................................... 50
7/11—Rev 0 to Rev A
Changes to Table 2, DAC CLOCK INPUT (DACCLK_P,
DACCLK_N), Added DAC Clock Rate..........................................4
Changes to Table 3, Added Dynamic Performance Parameters.......5
Change to Ordering Guide............................................................ 53
2/09—Revision 0: Initial Version
Rev. C | Page 4 of 49
5 Page 
AD9739
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDA, 3.3V, ANALOG SUPPLY
VSSA, ANALOG SUPPLY GROUND
VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD
Figure 2. Analog Supply Pins (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDD, 1.8V, DIGITAL SUPPLY
VSS DIGITAL SUPPLY GROUND
VDD33, 3.3V DIGITAL SUPPLY
Figure 3. Digital Supply Pins (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDC, 1.8V, CLOCK SUPPLY
VSSC, CLOCK SUPPLY GROUND
Figure 4. Digital LVDS Clock Supply Pins (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
DACCLK_N C
DACCLK_P D
E
F
G
H
SYNC_OUT_P/_N J
SYNC_IN_P/_N K
DB1[0:13]P L
DB1[0:13]N M
DB0[0:13]P N
DB0[0:13]N P
DCO_P/_N
DCI_P/_N
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
Figure 5. Digital LVDS Input, Clock I/O (Top View)
Rev. C | Page 10 of 49
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9739.PDF ] | |
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