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PDF ISL78228 Data sheet ( Hoja de datos )
| Número de pieza | ISL78228 | |
| Descripción | Dual 800mA Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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DATASHEET
Dual 800mA Low Quiescent Current 2.25MHz High
Efficiency Synchronous Buck Regulator
ISL78228
The ISL78228 is a high efficiency, dual synchronous step-down
DC/DC regulator that can deliver up to 800mA continuous
output current per channel. The supply voltage range of 2.75V
to 5.5V allows for the use of a 3.3V or 5V input. The current
mode control architecture enables very low duty cycle
operation at high frequency with fast transient response and
excellent loop stability. The ISL78228 operates above the AM
radio band as well as the 2.25MHz switching frequency,
allowing for the use of small, low cost inductors and
capacitors. Each channel is optimized for generating an output
voltage as low as 0.6V.
The ISL78228 has a user configurable mode of
operation-forced PWM mode and PFM mode. The forced PWM
mode operation reduces noise and RF interference while the
PFM mode operation provides high efficiency by reducing
switching losses at light loads. In PFM mode of operation, both
channels draw a total quiescent current of only 30µA, hence
enabling high light-load efficiency in order to maximize battery
life.
The ISL78228 offers a 1ms power-good (PG) to monitor both
outputs at power-up. When shut down, ISL78228 discharges
the output capacitor. Other features include internal digital
soft-start, enable for power sequence, overcurrent protection,
and thermal shutdown. The ISL78228 is offered in a
3mmx3mm 10 Ld DFN package with 1mm maximum height.
The complete converter occupies less than 1.8cm2 area.
The ISL78228 is AEC-Q100 qualified and is rated for the
automotive temperature range (-40°C to +105°C).
Features
• Internal current mode compensation
• 100% maximum duty cycle for lowest dropout
• Selectable forced PWM mode and PFM mode
• External synchronization up to 4MHz
• Start-up with prebiased output
• Soft-stop output discharge during disable
• Internal digital soft-start - 2ms
• Power-good (PG) output with 1ms delay
• AEC-Q100 qualified
• Pb-free (RoHS compliant)
Applications
• DC/DC POL modules
• µC/µP, FPGA and DSP power
• Rear camera systems
• Navigation systems
• Infotainment systems
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART
NUMBER
ISL78228
IOUT CH1
(A)
0.8
IOUT CH2
(A)
0.8
ADJ or FIXED
VOUT
PACKAGE
ADJ 10 Ld 3x3 DFN
ISL78322
2.0
1.7
ADJ 12 Ld 4x3 DFN
100
90
80 2.5VOUT-PFM
70 1.8VOUT-PFM
2.5VOUT-PWM
60
50
40
0.0
1.8VOUT- PWM
VIN = 5V
0.1 0.2
0.3 0.4 0.5
OUTPUT LOAD (A)
0.6
FIGURE 1. EFFICIENCY CHARACTERISTICS CURVE
0.7
0.8
February 26, 2016
FN7849.4
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013, 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL78228
Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating
conditions: TA = -40°C to +105°C, VIN = 2.75V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 2.2µH, C1 = 10µF, C2 = C4 = 10µF,
IOUT1 = IOUT2 = 0A to 800mA. (Typical values are at TA = +25°C, VIN = 3.6V). Boldface limits apply across the operating temperature range,
-40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6)
UNIT
LX_ Maximum Duty Cycle
100
PWM Switching Frequency
Synchronization Range
fSW
1.80
2.7
2.25
2.70
4
MHz
MHz
LX Minimum On-Time
SYNC = 0 (forced PWM mode)
100 ns
Soft Discharge Resistance
PG
RDIS_ EN = LOW
80 100 130
Ω
Output Low Voltage
Sinking 1mA, VFB = 0.5V
0.3 V
PG Pull-Up Resistor
1 mΩ
Internal PGOOD Low Rising Threshold
Percentage of nominal regulation voltage
88 92 96
mΩ
Internal PGOOD Low Falling Threshold
Percentage of nominal regulation voltage
82 89 91
%
Delay Time (Rising Edge)
1 ms
Internal PGOOD Delay Time (Falling Edge)
12
µs
EN1, EN2, SYNC
Logic Input Low
0.4 V
Logic Input High
1.4 V
SYNC Logic Input Leakage Current
Enable Logic Input Leakage Current
Thermal Shutdown
ISYNC
IEN_
Pulled up to 5.5V
0.1 1
0.1 1
150
µA
µA
°C
Thermal Shutdown Hysteresis
25 °C
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Submit Document Feedback
5
FN7849.4
February 26, 2016
5 Page 
ISL78228
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 2.75V to
5.5V, EN = VIN, L1 = L2 = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued)
LX1 2V/DIV
LX1 2V/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
IL1 0.5A/DIV
VOUT1 RIPPLE 20mV/DIV
200ns/DIV
FIGURE 33. CH1 STEADY STATE OPERATION AT NO LOAD (PFM) WITH
FREQUENCY = 4MHz
IL1 0.5A/DIV
VOUT1 RIPPLE 20mV/DIV
200ns/DIV
FIGURE 34. CH1 STEADY STATE OPERATION AT FULL LOAD (PFM)
WITH FREQUENCY = 4MHz
LX2 2V/DIV
LX2 2V/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
VOUT2 RIPPLE 20mV/DIV
IL2 0.5A/DIV
200ns/DIV
FIGURE 35. CH2 STEADY STATE OPERATION AT NO LOAD (PFM) WITH
FREQUENCY = 4MHz
IL2 0.5A/DIV
VOUT2 RIPPLE 20mV/DIV
200ns/DIV
FIGURE 36. CH2 STEADY STATE OPERATION AT FULL LOAD (PFM)
WITH FREQUENCY = 4MHz
LX1 5V/DIV
LX2 5V/DIV
SYNCH 5V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
100ns/DIV
FIGURE 37. CH1 AND CH2 STEADY STATE OPERATION AT NO LOAD
(PFM) WITH FREQUENCY = 4MHz
LX1 5V/DIV
LX2 5V/DIV
SYNCH 5V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
100ns/DIV
FIGURE 38. CH1 AND CH2 STEADY STATE OPERATION AT FULL LOAD
(PFM) WITH FREQUENCY = 4MHz
Submit Document Feedback 11
FN7849.4
February 26, 2016
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ISL78228.PDF ] | |
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