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PDF FM24CL16B Data sheet ( Hoja de datos )
| Número de pieza | FM24CL16B | |
| Descripción | 16Kb Serial 3V F-RAM Memory | |
| Fabricantes | Ramtron | |
| Logotipo |  |
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Preliminary
FM24CL16B
16Kb Serial 3V F-RAM Memory
Features
16K bit Ferroelectric Nonvolatile RAM
• Organized as 2,048 x 8 bits
• High Endurance 1014 Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
• Up to 1MHz Maximum Bus Frequency
• Direct Hardware Replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz
Low Power Operation
• 2.7 - 3.65V Operation
• 100 µA Active Current (100 kHz)
• 3 µA (typ.) Standby Current
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin “Green”/RoHS SOIC and TDFN Packages
Description
The FM24CL16B is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 38 years
while eliminating the complexities, overhead, and
system level reliability problems caused by EEPROM
and other nonvolatile memories.
The FM24CL16B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array in the cycle after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM24CL16B is capable of
supporting 1014 read/write cycles, or a million times
more write cycles than EEPROM.
These capabilities make the FM24CL16B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where a long write time
can cause data loss. The combination of features
allows the system to write data more frequently, with
less system overhead.
The FM24CL16B provides substantial benefits to
users of serial EEPROM, yet these benefits are
available in a hardware drop-in replacement. The
FM24CL16B is available in an industry standard 8-
pin SOIC package and uses a familiar two-wire
protocol. The specifications are guaranteed over the
industrial temperature range from -40°C to +85°C.
Pin Configuration
NC 1 8 VDD
NC 2 7 WP
NC 3 6 SCL
VSS 4 5 SDA
Top View
NC 1
NC 2
NC 3
VSS 4
8 VDD
7 WP
6 SCL
5 SDA
Pin Names
SDA
SCL
WP
VDD
VSS
Function
Serial Data/Address
Serial Clock
Write Protect
Supply Voltage
Ground
Ordering Information
FM24CL16B-G
“Green”/RoHS 8-pin SOIC
FM24CL16B-GTR
“Green”/RoHS 8-pin SOIC,
Tape & Reel
FM24CL16B-DG
“Green”/RoHS 8-pin TDFN
FM24CL16B-DGTR “Green”/RoHS 8-pin TDFN,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.4
Feb. 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 13
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1 page  
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FM24CL16B - 16Kb 3V I2C F-RAM
Slave ID
Page
Select
1 0 1 0 A2 A1 A0 R/W
Figure 4. Slave Address
Word Address
After the FM24CL16B (as receiver) acknowledges
the slave ID, the master will place the word address
on the bus for a write operation. The word address is
the lower 8-bits of the address to be combined with
the 3-bits of the page select to specify the exact byte
to be written. The complete 11-bit address is latched
internally.
No word address occurs for a read operation, though
the 3-bit page select is latched internally. Reads
always use the lower 8-bits that are held internally in
the address latch. That is, reads always begin at the
address following the previous access. A random read
address can be loaded by doing a write operation as
explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24CL16B increments the
internal address latch. This allows the next sequential
byte to be accessed with no additional addressing.
After the last address (7FFh) is reached, the address
latch will roll over to 000h. There is no limit on the
number of bytes that can be accessed with a single
read or write operation.
Data Transfer
After all address information has been transmitted,
data transfer between the bus master and the
FM24CL16B can begin. For a read operation the
device will place 8 data bits on the bus then wait for
an acknowledge. If the acknowledge occurs, the next
sequential byte will be transferred. If the
acknowledge is not sent, the read operation is
concluded. For a write operation, the FM24CL16B
will accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most
significant bit) first.
Memory Operation
The FM24CL16B is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24CL16B and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave ID then a word address
as previously mentioned. The bus master indicates a
write operation by setting the LSB of the Slave
Address to a 0. After addressing, the bus master
sends each byte of data to the memory and the
memory generates an acknowledge condition. Any
number of sequential bytes may be written. If the
end of the address range is reached internally, the
address counter will wrap from 7FFh to 000h.
Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a ‘ready’ condition.
An actual memory array write occurs after the 8th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition
prior to the 8th data bit. The FM24CL16B needs no
page buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL16B will not acknowledge data bytes that
are written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature.
Figure 5 and 6 below illustrates both a single-byte
and multiple-byte writes.
Rev. 1.4
Feb. 2011
Page 5 of 13
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5 Page 
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Mechanical Drawing
8-pin SOIC (JEDEC MS-012 variation AA)
FM24CL16B - 16Kb 3V I2C F-RAM
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXXXP
RLLLLLLL
RICYYWW
Legend:
XXXXXX= part number, P= package type (G=SOIC)
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM24CL16B, “Green” SOIC package, Year 2010, Work Week 49
FM24CL16BG
A00002G1
RIC1049
Rev. 1.4
Feb. 2011
Page 11 of 13
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FM24CL16B.PDF ] | |
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