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PDF CY29949 Data sheet ( Hoja de datos )
| Número de pieza | CY29949 | |
| Descripción | 1:15 Clock Distribution Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY29949
2.5V or 3.3V 200 MHz 1:15
Clock Distribution Buffer
Features
■ 2.5V or 3.3V operation
■ 200-MHz clock support
■ LVPECL or LVCMOS/LVTTL clock input
■ LVCMOS/LVTTL compatible outputs
■ 15 clock outputs: drive up to 30 clock lines
■ 1X and 1/2X configurable outputs
■ Output three-state control
■ 350 ps maximum output-to-output skew
■ Pin compatible with MPC949, MPC9449
■ Available in Commercial and Industrial temperature range
■ 52-pin TQFP package
Logic Block Diagram
Description
The CY29949 is a low voltage 200 MHz clock distribution
buffer with the capability to select either a differential LVPECL
or LVCMOS/LVTTL compatible input clocks. These clock
sources are used to provide for test clocks and primary system
clocks. All other control inputs are LVCMOS/LVTTL
compatible. The 15 outputs are LVCMOS or LVTTL compatible
and can drive 50Ω series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals
from a 1X source. These signals are generated and retimed
internally to ensure minimal skew between the 1X and 1/2X
signals. SEL(A:D) inputs allow flexibility in selecting the ratio
of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the
MR/OE# input. When MR/OE# is set HIGH, it resets the
internal flip-flops and three-states the outputs.
TCLK_SEL
PECL_CLK
PECL_CLK#
PECL_SEL
0
1
0
1
DSELA
DSELB
DSELC
DSELD
MR/OE#
1
R2
0
1
1
R2
0
1
1
R2
0
1
1
R2
0
1
2 QA(0:1)
3 QB(0:2)
4 QC(0:3)
6 QD(0:5)
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .3n8et-07289 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 22, 2008
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1 page  
Figure 4. Propagation Delay (TPD) Test Reference
PECL_CLK
PECL_CLK
VPP
VCMR
Q
tPD
VCC
VCC /2
GND
Figure 5. LVCMOS Propagation Delay (TPD) Test Reference
LVCMOS_CLK
Q
tPD
VCC
VCC /2
GND
VCC
VCC /2
GND
Figure 6. Output Duty Cycle (FoutDC)
VCC
tP
T0
VCC /2
GND
DC = tP / T0 x 100%
Figure 7. Output-to-Output Skew tsk(0)
tSK(0)
VCC
VCC /2
GND
VCC
VCC /2
GND
CY29949
Document #: 38-07289 Rev. *E
Page 5 of 7
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CY29949.PDF ] | |
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