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PDF LS841 Data sheet ( Hoja de datos )
| Número de pieza | LS841 | |
| Descripción | Low Noise | |
| Fabricantes | Micross | |
| Logotipo |  |
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LS841
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
The LS841 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS841 features a 10-
mV offset and 10-µV/°C drift.
FEATURES
LOW DRIFT
| V GS1‐2 / T| ≤10µV/°C
LOW LEAKAGE
IG = 10pA TYP.
LOW NOISE
en = 8nV/√Hz TYP.
LOW OFFSET VOLTAGE
| V GS1‐2| ≤10mV
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
LS841 Applications:
Maximum Temperatures
Storage Temperature
‐65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐VGSS
Gate Voltage to Drain or Source
‐VDSO
Drain to Source Voltage
‐IG(f) Gate Forward Current
Maximum Power Dissipation
60V
60V
50mA
Wideband Differential Amps
High-Speed,Temp-Compensated Single-
Ended Input Amps
High-Speed Comparators
Impedance Converters and vibrations
detectors.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
Device Dissipation @ Free Air – Total 400mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V GS1‐2 / T| max.
| V GS1‐2 | max.
DRIFT VS.
TEMPERATURE
OFFSET VOLTAGE
10 µV/°C VDG=20V, ID=200µA
TA=‐55°C to +125°C
10 mV VDG=20V, ID=200µA
SYMBOL
CHARACTERISTICS
MIN.
BVGSS
Breakdown Voltage
60
BVGGO
Gate‐To‐Gate Breakdown
60
TRANSCONDUCTANCE
YfSS
YfS
|YFS1‐2 / Y FS|
ClickIDSS
Full Conduction
Typical Operation
Mismatch
DRAIN CURRENT
Full Conduction
1000
500
‐‐
0.5
|IDSS1‐2 / IDSS| Mismatch at Full Conduction
‐‐
GATE VOLTAGE
VGS(off) or Vp
VGS(on)
Pinchoff voltage
Operating Range
1
0.5
GATE CURRENT
‐IGmax.
Operating
‐‐
‐IGmax.
High Temperature
‐‐
‐IGmax.
Reduced VDG
‐‐
‐IGSSmax.
At Full Conduction
OUTPUT CONDUCTANCE
‐‐
YOSS Full Conduction ‐‐
YOS Operating ‐‐
|YOS1‐2|
Differential
‐‐
COMMON MODE REJECTION
CMR
‐20 log | V GS1‐2/ V DS|
‐‐
‐20 log | V GS1‐2/ V DS|
‐‐
NOISE
NF Figure ‐‐
en
Voltage
‐‐
‐‐
CAPACITANCE
CISS Input ‐‐
CRSS Reverse Transfer ‐‐
CDD Drain‐to‐Drain ‐‐
TYP. MAX.
UNITS
CONDITIONS
60 ‐‐
V
VDS = 0 ID=1nA
‐‐ ‐‐
V I G= 1nA ID= 0 IS= 0
To Buy‐‐ 4000
‐‐ 1000
0.6 3
2 5
µmho
µmho
%
mA
VDG= 20V VGS= 0V f = 1kHz
VDG= 20V ID= 200µA
VDG= 20V VGS= 0V
1 5
%
2 4.5
‐‐ 4
V VDS= 20V ID= 1nA
V VDS=20V ID=200µA
10 50
pA
VDG= 20V ID= 200µA
‐‐ 50
nA TA= +125°C
5 ‐‐
pA
VDG = 10V ID= 200µA
‐‐ 100
pA
VDG= 20V , VDS =0
‐‐ 10
0.1 1
µmho
µmho
VDG= 20V VGS= 0V
VDG= 20V ID= 200µA
0.01
0.1
µmho
100 ‐‐
dB
∆VDS = 10 to 20V ID=200µA
75 ‐‐
∆VDS = 5 to 10V ID=200µA
VDS= 20V VGS= 0V RG= 10MΩ
‐‐ 0.5
dB
f= 100Hz NBW= 6Hz
‐‐ 10
nV/√Hz
VDS=20V ID=200µA f=1KHz NBW=1Hz
‐‐ 15
VDS=20V ID=200µA f=10Hz NBW=1Hz
10
4
1.2 5
pF
VDS= 20V, ID=200µA
0.1 ‐‐
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP & SOIC (Top View)
Available Packages:
LS841 / LS841 in PDIP & SOIC
LS841 / LS841 available as bare die
Please contact Micross for full package and die dimensions
Tel: +44 1603 788967
Email: [email protected]
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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