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PDF CY62137FV18 Data sheet ( Hoja de datos )

Número de pieza CY62137FV18
Descripción 2-Mbit (128K x 16) Static RAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CY62137FV18 MoBL®
2-Mbit (128K x 16) Static RAM
Features
Very high speed: 55 ns
Wide voltage range: 1.65 V – 2.25 V
Pin compatible with CY62137CV18
Ultra low standby power
Typical standby current: 1 A
Maximum standby current: 5 A
Ultra low active power
Typical active current: 1.6 mA @ f = 1 MHz
Ultra low standby power
Easy memory expansion with CE and OE features
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Byte power-down feature
Available in a Pb-free 48-Ball Very fine ball grid package
(VFBGA) package
Functional Description
The CY62137FV18 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both the Byte High
Enable and the Byte Low Enable are disabled (BHE, BLE HIGH),
or during an active write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A16).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from the memory
appears on I/O8 to I/O15. See the “Truth Table” on page 11 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A10
A9
A8
A7
AA65
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K x 16
RAM Array
COLUMN DECODER
POWER DOWN
CIRCUIT
CE
BHE
BLE
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-08030 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 15, 2010
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CY62137FV18 pdf
CY62137FV18 MoBL®
Thermal Resistance
Parameter[10]
Description
JA Thermal resistance
(Junction to Ambient)
JC Thermal resistance
(Junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
VFBGA
75
10
Unit
C / W
C / W
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
Figure 2. AC Test Loads and Waveforms
ALL INPUT PULSES
VCC
10%
90%
GND
R2 Rise Time = 1 V/ns
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
R1
R2
RTH
VTH
1.80 V
13500
10800
6000
0.80
Unit
V
Note
10. Tested initially and after any design or process changes that may affect these parameters
Document #: 001-08030 Rev. *H
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CY62137FV18 arduino
CY62137FV18 MoBL®
Truth Table
CE
H
X[29]
L
L
WE
X
X
H
H
LH
LH
LH
LH
LL
LL
LL
OE BHE BLE
Inputs or Outputs
X X[29] X[29] High Z
X H H High Z
L L L Data out (I/O0–I/O15)
L H L Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
H L L High Z
H H L High Z
H L H High Z
X L L Data in (I/O0–I/O15)
X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Mode
Deselect or power down
Deselect or power down
Read
Read
Read
Output disabled
Output dsabled
Output disabled
Write
Write
Write
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Note
29. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate
voltage levels on these pins is not permitted
Document #: 001-08030 Rev. *H
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