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PDF CY62136V Data sheet ( Hoja de datos )
| Número de pieza | CY62136V | |
| Descripción | 2-Mbit (128K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62136V MoBL®
2-Mbit (128K x 16) Static RAM
Features
• Temperature Ranges
— Commercial : 0°C to 70°C
— Industrial : −40°C to 85°C
— Automotive : −40°C to 125°C
• High speed: 55 ns and 70 ns
• 70-ns speed bin offered in both Industrial and
Automotive grades
• Wide voltage range: 2.7V-3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a standard 44-pin TSOP Type II
(forward pinout) package
Functional Description[1]
The CY62136V is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH). The input/output pins (I/O0 through
I/O15) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5 128K x 16
A4 RAM Array
A3 2048 x 1024
A2
A1
A0
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05087 Rev. *B
Revised September 24, 2004
www.DataSheet.in
1 page  
CY62136V MoBL®
Switching Characteristics Over the Operating Range (continued)[8]
Parameter
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[11, 12]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Description
OE HIGH to High-Z[9, 10]
CE LOW to Low-Z[9]
CE HIGH to High-Z[9, 10]
CE LOW to Power-up
CE HIGH to Power-down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low-Z[9, 10]
BLE / BHE HIGH to High-Z[11]
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9, 10]
WE HIGH to Low-Z[9]
55 ns
Min.
Max.
25
10
25
0
55
25
5
25
55
45
45
0
0
40
50
25
0
20
5
Switching Waveforms
Read Cycle No. 1[13, 14]
tRC
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
70 ns
Min.
Max.
25
10
25
0
70
35
5
25
70
60
60
0
0
50
60
30
0
25
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA VALID
Notes:
11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
12. The minimum write cycle time for write cycle 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycle.
Document #: 38-05087 Rev. *B
www.DataSheet.in
Page 5 of 11
5 Page 
CY62136V MoBL®
Document History Page
Document Title: CY62136V MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 38-05087
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
107347
05/25/01
SZV Changed from Spec #: 38-00728 to 38-05087
*A
116509
09/04/02
GBI Added footnote 1
Added SL power bin
Deleted fBGA package; replacement fBGA package available in
CY62136CV30
*B
269729
See ECN
SYT Added Automotive Information for 70-ns Speed Bin.
Added Footnotes # 3 and # 6.
Corrected Typo in Electrical Characteristics for ICC(Max)-55 ns from 15 to
20 mA.
Added SL row for ISB2 in the Electrical Characteristics table.
Changed Package Name from Z44 to ZS44.
Replaced ‘Z’ with ‘ZS’ in the Ordering Code.
Document #: 38-05087 Rev. *B
www.DataSheet.in
Page 11 of 11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CY62136V.PDF ] | |
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