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PDF LTC5587 Data sheet ( Hoja de datos )
| Número de pieza | LTC5587 | |
| Descripción | 6GHz RMS Power Detector | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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DataSheet.in
LTC5587
6 GHz RMS Power Detector
with Digital Output
FEATURES
n Frequency Range: 10MHz to 6GHz
n Accurate Power Measurement of High Crest Factor
(Up to 12dB) Waveforms
n 40dB Log Linear Dynamic Range
n Exceptional Accuracy Over Temperature
n Single-Ended RF Input
n 0.014dB/Bit (12-Bit) ADC Resolution (VREF = 1.8V)
n ADC Sample Rate Up to 500ksps
n SPI/MICROWIRE Serial I/O
n Compatible with 1V to 3.6V Digital Logic
n Fast Response Time: 1μs Rise, 8μs Fall
n Low Power: 3mA at 3.3V and 500ksps
n Small 3mm × 3mm 12-pin DFN Package
APPLICATIONS
n LTE, WiMAX, W-CDMA, TD-SCDMA, CDMA,
CDMA2000, EDGE, GSM
n Pico-Cells, Femto-Cells RF Power Control
n Wireless Repeaters
n CATV/DVB Transmitters
n MIMO Wireless Access Points
n Portable RMS Power Measurement
n Antenna Monitor
DESCRIPTION
The LTC®5587 is a 10MHz to 6GHz, low power monolithic
precision RMS power detector with an integrated 12-bit
serial analog-to-digital converter (ADC). The RMS detec-
tor uses a proprietary technique to accurately measure the
RF power of modulated signals with crest-factor as high
as 12dB. For an input frequency of 2.14GHz the detection
range is from –34dBm to 6dBm. The serial digital output
of the detector is a 12-bit word value that is directly pro-
portional to the RF signal power measured in dBm. The
LTC5587 is suitable for precision power measurement
for a wide variety of RF standards, including LTE, WiMAX,
W-CDMA, TD-SCDMA, CDMA, CDMA2000, EDGE, GSM,
etc. The DC output of the detector is connected in series
with an on-chip 300Ω resistor to the analog output pin
(VOUT). This enables further filtering of the output modu-
lation ripple using an off-chip capacitor before analog-to-
digitalconversion. TheADCfeaturesincludenodatalatency,
no missing codes, and a sampling rate of up to 500ksps. A
dedicated external reference pin (VREF) can be tied to VDD
orother suitable low-impedance voltage reference to set the
ADC full-scale input voltage range. The ADC also features
an automatic power down after each conversion making
the LTC5587 ideal for low-power applications.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
BLOCK DIAGRAM
RF
7
13
EXPOSED
PAD
150kHz LPF
RMS
DETECTOR
OUTPUT
BUFFER
300Ω
4
VOUT
S/H
BIAS
6 CSQ
EN
9
8 VCC
GND
5
11
VDD
3
OVDD
12-BIT ADC
THREE-STATE
SERIAL OUTPUT
PORT
SDO
1
10 VREF
TIMING
LOGIC
SCK
2
CONV
12
5587 BD
Linearity Error vs RF Input Power
2140MHz Modulated Waveforms
3
TA = 25°C
2
1
0
–1 CW
WCDMA, UL
WCDMA DL 1C
–2 WCDMA DL 4C
LTE DL 1C
LTE DL 4C
–3
–35 –30 –25 –20 –15 –10 –5
0
RF INPUT POWER (dBm)
5 10
5587 G12
5587f
1
1 page  
DataSheet.in
LTC5587
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL =
fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1.
SYMBOL
PARAMETER
CIN SCK, CONV Input Capacitance
VOH SDO Logic High Output
VOL SDO Logic Low Output
IOZ Hi-Z Output Leakage
COZ Hi-Z Output Capacitance
ISOURCE
SDO Source Current
ISINK SDO Sink Current
Detector Enable (EN) Low = Off, High = On
PARAMETER
EN Input High Voltage (On)
EN Input Low Voltage (Off)
Enable Pin Input Current
Turn ON Time; CW RF Input
Turn OFF Time; CW RF Input
Power Supply
OVDD Supply Voltage
VDD Supply Voltage
VREF Reference Voltage
VCC Supply Voltage
Total Supply Current
Shutdown Current
CONDITIONS
ISOURCE = 200μA
ISINK = 200μA
CONV = VDD
CONV = VDD
SDO Connected to GND = 0V
SDO Connected to VDD
CONDITIONS
EN = 3.3V
VOUT within 10% of Final Value; PIN = 0dBm
VOUT < 0.18V; PIN = 0dBm
Should Be Equal to VDD
No RF Input Signal, ADC Operational at 500ksps
No RF Input Signal, ADC Sleep-Mode
EN = 0.3V, CONV = 3.3V, ADC Sleep-Mode
MIN
l VDD – 0.2
l
l
TYP
2
4
–10
10
MAX
0.2
±3
MIN
l2
l
TYP
25
1
8
MAX
0.3
l1
l 2.7
l 1.4
l 2.7
l
l
3.3 VDD
3.3 3.6
VDD + 0.05
3.3 3.6
34
1.4 2.5
0.2 10
UNITS
pF
V
V
μA
pF
mA
mA
UNITS
V
V
μA
μs
μs
V
V
V
V
mA
mA
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. The maximum RF input power rating is guaranteed
by design and engineering characterization, but not production tested.
Note 2: The LTC5587 is guaranteed to be functional over the operating
temperature range from –40°C to 85°C.
Note 3: The linearity error is calculated by the difference between the
incremental slope of the output and the average output slope from –20dBm
to 0dBm. The dynamic range is defined as the range over which the
linearity error is within ±1dB.
Note 4: An external capacitor at the CSQ pin should be used for input
frequencies below 250MHz. Without this capacitor, lower frequency
operation results in excessive RF ripple in the output voltage.
Note 5: Logarithmic intercept is an extrapolated input power level from
the best fitted log-linear straight line, where the converted output code is
0LSB.
Note 6: PSRR determined as the dB value of the change in converted
output voltage over the change in VCC supply voltage at a given CW input
power level.
Note 7: Guaranteed by design not subject to test.
Note 8: Guaranteed by characterization. All input signals are specified with
tR = tF = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 9: All timing specifications given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: The time required for the output to cross the VIH or VIL voltage.
Note 11: When pins VOUT and VREF are taken below GND or above VDD,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below GND or above VDD without latchup.
Note 12: The VDD supply voltage can be the same as VCC and the pins can
share a common bypass capacitor of 2.2μF.
5587f
5
5 Page 
DataSheet.in
TIMING DIAGRAMS
SDO Into Hi-Z State After CONV Rising Edge
CONV
SDO
t8
1.6V
Hi-Z
5587 TD01
SDO Data Valid Hold Time After SCK Falling Edge
SCK
SDO VIH
VIL
t7
1.6V
5587 TD02
SDO Data Valid Access Time After SCK Falling Edge
t4
SCK 1.6V
SDO
VIH
VIL
5587 TD03
LTC5587
5587f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC5587.PDF ] | |
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