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PDF LT3748 Data sheet ( Hoja de datos )
| Número de pieza | LT3748 | |
| Descripción | 100V Isolated Flyback Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Features
nn 5V to 100V Input Voltage Range
nn 1.9A Average Gate Drive Source and Sink Current
nn Boundary Mode Operation
nn No Transformer Third Winding or Opto-Isolator
Required for Regulation
nn Primary-Side Winding Feedback Load Regulation
nn VOUT Set with Two External Resistors
nn INTVCC Pin for Control of Gate Driver Voltage
nn Programmable Soft Start
nn Programmable Undervoltage Lockout
nn Available in MSOP Package
Applications
nn Isolated Telecom Converters
nn High Power Automotive Supplies
nn Isolated Industrial Power Supplies
nn Military and High Temperature Applications
LT3748
100V Isolated
Flyback Controller
Description
The LT®3748 is a switching regulator controller specifically
designed for the isolated flyback topology and capable of
high power. It drives a low side external N-channel power
MOSFET from an internally regulated 7V supply. No third
winding or opto-isolator is required for regulation as the
part senses the isolated output voltage directly from the
primary-side flyback waveform.
The LT3748 utilizes boundary mode to provide a small
magnetic solution without compromising load regulation.
Operating frequency is set by load current and transformer
magnetizing inductance. The gate drive of the LT3748
combined with a suitable external MOSFET allow it to
deliver load power up to several tens of watts from input
voltages as high as 100V.
The LT3748 is available in a high voltage 16-lead MSOP
package with four leads removed.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5438499 and 7471522.
Typical Application
25W, 12V Output, Isolated Telecom Supply
VIN
36V TO 72V
4:1
10µF
412k
EN/UVLO VIN
15.4k
LT3748
RFB
RREF
60.8µH
243k
6.04k
3.8µH
56.2k
TC GATE
SS SENSE
VC GND INTVCC
2nF 10k
4700pF
4.7µF
0.033Ω
3748 TA01a
VOUT+
12V
2A
100µF
VOUT–
Output Load and Line Regulation
12.6
12.4
12.2
12.0
11.8
11.6
11.4
0
VIN = 72V
VIN = 48V
VIN = 36V
0.5 1.0 1.5
LOAD CURRENT (A)
2.0
3748 TA01b
For more information www.linear.com/LT3748
3748fb
1
1 page  
LT3748
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
EN/UVLO Current vs Temperature
3.0
2.5 VEN/UVLO = 1.1V
2.0 VEN/UVLO = 0.9V
1.5
1.0
0.5
0
–55 –25
VEN/UVLO = 1.3V
0 25 50 75 100 125 150
TEMPERATURE (°C)
3748 G10
Error Amplifier Transconductance
vs Temperature
200
190
180
170
160
150
140
130
120
110
100
–55 –25
VIN = 100V
VIN = 6V
0 25 50 75 100 125 150
TEMPERATURE (°C)
3748 G13
Maximum Discontinuous Off-Time
vs Temperature
30
29
28
27
26
25
24
23
22
21
20
–55 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3748 G16
EN/UVLO Threshold
vs Temperature
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
–55 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3748 G11
Error Amplifier Output Current
vs RREF Pin Voltage
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
0
150°C
100°C
25°C
–50°C
0.5 1.0 1.5 2.0 2.5
VREF (V)
3748 G14
GATE Rise and Fall Time vs Charge
2.0
AVERAGE
1.5
CURRENT
50 1.0
40
30
20
10
0
0
RISE TIME
FALL TIME
0.5
0
Q=C•V
VINTVCC = 7V
tr, tf 10% TO 90%
20 40 60 80 100 120
TOTAL GATE CHARGE (nC)
3748 G17
For more information www.linear.com/LT3748
TC Pin Voltage vs Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–55 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3748 G12
SENSE Pin Threshold
vs Temperature
160
140 OVERCURRENT
120
100 VC = 2.2V
80
60
40
20 VC = 0.2V
0
–55 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3748 G15
GATE Rise and Fall Time
vs INTVCC Voltage
25 CGATE = 3.3nF
tr, tf 10% TO 90%
20 FALLING
15 RISING
10
5
0
0 5 10 15 20
VINTVCC (V)
3748 G18
3748fb
5
5 Page 
LT3748
Applications Information
Minimum Primary Inductance Requirements
The LT3748 obtains output voltage information from the
external MOSFET drain voltage when the secondary winding
conducts current. The sampling circuitry needs a minimum
of 400ns to settle and sample the output voltage while the
MOSFET switch is off. This required settle and sample
time is controlled by external components independent of
the minimum off-time of the GATE pin as specified in the
Electrical Characteristics table. The electrical specification
minimum off-time is based on an internal timer and acts
as a maximum frequency clamp. The following equation
gives the minimum value for primary-side magnetizing
inductance:
( )LPRI ≥
VOUT + VF(DIODE) • RSENSE • tSETTLE(MIN) • NPS
VSENSE(MIN)
VSENSE(MIN) = 15mV
tSETTLE(MIN) = 400ns
NPS = Ratio of primary windings to secondary windings
In addition to the primary inductance requirement for
minimum settling and sampling time, the LT3748 has
internal circuit constraints that prevent it from setting the
GATE node high for shorter than approximately 250ns.
If the inductor current exceeds the desired current limit
during that time oscillation may occur at the output as
the current control loop will lose its ability to regulate.
Therefore, the following equation relating to maximum
input voltage must also be followed in selecting primary-
side magnetizing inductance:
LPRI
≥
VIN(MAX) • RSENSE • tON(MIN)
VSENSE(MIN)
Output Power
Because the MOSFET power switch is located outside the
LT3748, the maximum output power is primarily limited
by external components. Output power limitations can
be separated into three categories—voltage limitations,
current limitations and thermal limitations.
The voltage limitations in a flyback design are primar-
ily the MOSFET switch VDS(MAX) and the output diode
reverse-bias rating. Increasing the voltage rating of either
component will typically decrease application efficiency if
all else is equal and the voltage requirements on each of
those components will be directly related to the windings
ratio of the transformer, the input and output voltages
and the use of any additional snubbing components.
The MOSFET VDS(MAX) must theoretically be higher than
VIN(MAX) + (VOUT • NPS) and the output diode reverse bias
must be higher than VOUT + (VIN(MAX)/NPS), though leak-
age inductance spikes on both the drain of the MOSFET
and the anode of the output diode may more than double
that requirement (see section on leakage inductance for
more details on snubbers). Figure 1 illustrates the effect
on available output power for several MOSFET voltage
ratings while continuously maximizing windings ratio
for input voltage with a fixed MOSFET current limit and
output voltage. Increasing the MOSFET rating increases
the possible windings ratio and or maximum input voltage
and can increase the available output power for a given
application. Both figures assume no leakage inductance
and high efficiency.
50
VDS = 200V
40 VDS = 150V
tON(MIN) = 250ns
30
The last constraint on minimum inductance value would
relate to minimum full-load operating frequency, fSW(MIN),
and is derived from fSW = 1/(tON + tOFF):
LPRI ≤ VIN(MIN) • (VOUT + VF(DIODE)) • NPS/(fSW(MIN) • ILIM •
((VOUT + VF(DIODE)) • NPS + VIN(MIN)))
The minimum operating frequency may be lower than
the calculated number due to delays in detecting current
limit and detecting boundary mode that are specific to
each application.
VDS = 100V
20
10
0
0 20 40 60 80 100
INPUT VOLTAGE (V)
3748 F01
3FAiguILrIeM1a.nMd aMxaimxiummumOuVtpDuSt=P1o0w0eVr,a1t5102VV,O2U0T0wVith a
3748fb
For more information www.linear.com/LT3748
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LT3748.PDF ] | |
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