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PDF LTC4219 Data sheet ( Hoja de datos )
| Número de pieza | LTC4219 | |
| Descripción | 5A Integrated Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n Small Footprint
n 33mΩ MOSFET with RSENSE
n Available in Preset 12V and 5V Versions
n Adjustable, 10% Accurate Current Limit
n Current and Temperature Monitor Outputs
n Overtemperature Protection
n Adjustable Current Limit Timer Before Fault
n Power Good and Fault Outputs
n Adjustable Inrush Current Control
n Available in 16-Lead 5mm × 3mm DFN Packages
APPLICATIONS
n RAID Systems
n Server I/O Cards
n Industrial
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LTC4219
5A Integrated
Hot Swap Controller
DESCRIPTION
The LTC®4219 is an integrated solution for Hot Swap™
applications that allows a board to be safely inserted and
removed from a live backplane. The part integrates a Hot
Swap controller, power MOSFET and current sense resistor
in a single package for small form factor applications.
The LTC4219 provides separate inrush current control
and a 10% accurate 5.6A current limit with foldback cur-
rent limiting. The current limit threshold can be adjusted
dynamically using an external pin. Additional features
include a current monitor output that amplifies the sense
resistor voltage for ground referenced current sensing
and a MOSFET temperature monitor output. Thermal limit
and power good monitoring are also provided. The power
good detection level and foldback current limit profile are
internally preset for 5V (LTC4219-5) and 12V (LTC4219-12)
applications.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of
their respective owners.
TYPICAL APPLICATION
12V, 5A Card Resident Application
VOUT
12V
VDD OUT
12V
12V + 5A
LTC4219DHC-12
10k 12V
330μF
EN1 PG
10k
EN2 FLT
TIMER
ISET
INTVCC
0.1μF
GND
IMON
ADC
20k
4219 TA01a
VIN
10V/DIV
IIN
0.1A/DIV
VOUT
10V/DIV
PG
10V/DIV
Power-Up Waveforms
20ms/DIV
4219 TA01b
4219f
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LTC4219
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 12V unless otherwise noted.
EN1, EN2 Hysteresis
vs Temperature
0.10
Timer Pull-Up Current
vs Temperature
–110
Current Limit Delay
(tPHL(ILIM) vs Overdrive)
1000
–105
0.08
–100
0.06
–95
100
10
1
0.04
–50
–25 0 25 50
TEMPERATURE (°C)
75 100
4219 G04
Current Limit Threshold Foldback,
LTC4219-5
6
5
4
3
2
1
0
012345
VOUT (V)
4219 G07
–90
–50
–25 0 25 50
TEMPERATURE (°C)
75 100
4219 G05
Current Limit Threshold Foldback,
LTC4219-12
6
5
4
3
2
1
0
0 3 6 9 12
VOUT (V)
4219 G08
0.1
0
10 20
OUTPUT CURRENT (A)
30
4219 G06
Current Limit Adjustment
(IOUT vs RSET)
6
5
4
3
2
1
0
1k 10k 100k 1M 10M
RSET (Ω)
4219 G09
ISET Resistor vs Temperature
22
21
20
19
18
–50
–25 0 25 50
TEMPERATURE (°C)
75 100
4219 G10
RON vs VDD and Temperature
60
50
VDD = 3.3V, 12V
40
30
20
10
0
–50 –25
0
25 50
TEMPERATURE (°C)
75 100
4219 G11
MOSFET SOA Curve
10
1
0.1
TA = 25°C
MULTIPLE PULSE
DUTY CYCLE = 0.2
0.01
0.1 1
VDS (V)
10
1ms
10ms
100ms
1s
10s
DC
100
4219 G12
4219f
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LTC4219
APPLICATIONS INFORMATION
Adding a capacitor and a 1k series resistor from GATE
to ground will lower the inrush current below the default
value set by the inrush circuit. The GATE is then charged
with a 24μA current source. The voltage at the GATE pin
rises with a slope equal to 24μA/CGATE and the supply
inrush current is set at:
IINRUSH
=
CL
CGATE
• 24µA
When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the OUT volt-
age follows the GATE voltage as it increases. Once OUT
reaches VDD, the GATE will ramp up until clamped by the
6.15V Zener between GATE and OUT.
As the OUT voltage rises, so will the FB pin which is moni-
toring it. Once the FB pin crosses its 1.235V threshold and
the GATE to OUT voltage exceeds 4.2V, the PG pin pulls
low indicating that the power is good.
Parasitic MOSFET Oscillation
When the N-channel MOSFET ramps up the output dur-
ing power-up it operates as a source follower. The source
follower configuration may self-oscillate in the range of
25kHz to 300kHz when the load capacitance is less than
10μF, especially if the wiring inductance from the supply
to the VDD pin is greater than 3μH. The possibility of oscil-
lation will increase as the load current (during power-up)
increases. There are two ways to prevent this type of
oscillation. The simplest way is to avoid load capacitances
below 10μF. For wiring inductance larger than 20μH, the
minimum load capacitance may extend to 100μF. A second
choice is to connect an external gate capacitor CP >1.5nF
as shown in Figure 3.
GATE
LTC4219
CP
2.2nF
* OPTIONAL
RC TO LOWER
INRUSH CURRENT
4219 F03
Figure 3. Compensation for Small CLOAD
Turn-Off Sequence
The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by either the EN1 or EN2 pins
going above their 1.235V threshold. Additionally, several
fault conditions will turn off the switch. These include
overcurrent circuit breaker (SENSE pin) or overtem-
perature. Normally the switch is turned off with a 250μA
current pulling down the GATE pin to ground. With the
switch turned off, the OUT voltage drops which pulls the
FB pin below its threshold. PG then goes high to indicate
output power is no longer good.
If VDD drops below 2.65V for greater than 5μs or INTVCC
drops below 2.5V for greater than 1μs, a fast shutdown
of the switch is initiated. The GATE is pulled down with a
170mA current to the OUT pin.
Overcurrent Fault
The LTC4219 features an adjustable current limit with
foldback that protects against short circuits or excessive
load current. To prevent excessive power dissipation in the
switch during active current limit, the available current is
reduced as a function of the output voltage sensed by the
FB pin. A graph in the Typical Performance Characteristics
curves shows the current limit versus FB voltage.
An overcurrent fault occurs when the current limit circuitry
has been engaged for longer than the time-out delay set
by the TIMER. Current limiting begins when the MOSFET
current reaches 1.5A to 5.6A (depending on the foldback).
The GATE pin is then brought down with a 140mA GATE-
to-OUT current. The voltage on the GATE is regulated in
order to limit the current to less than 5.6A. At this point,
a circuit breaker time delay starts by charging the external
timing capacitor from the TIMER pin with a 100μA pull-
up current. If the TIMER pin reaches its 1.2V threshold,
the internal switch turns off (with a 250μA current from
GATE to ground). Included in the Typical Performance
Characteristics curves is a graph of the Safe Operating
Area for the MOSFET. From this graph one can determine
the MOSFET’s maximum time in current limit for a given
output power.
4219f
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC4219.PDF ] | |
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