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PDF TZA3026 Data sheet ( Hoja de datos )
| Número de pieza | TZA3026 | |
| Descripción | SDH/SONET STM4/OC12 transimpedance amplifer | |
| Fabricantes | NXP Semiconductors | |
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TZA3026
www.DataSheet4U.com
SDH/SONET STM4/OC12 transimpedance amplifier
Rev. 01 — 2 May 2005
Product data sheet
1. General description
The TZA3026 is a transimpedance amplifier with Automatic Gain Control (AGC), designed
to be used in STM4/OC12 fiber optic links. It amplifies the current generated by a photo
detector (PIN diode or avalanche photodiode) and converts it to a differential output
voltage. It offers a current mirror of average photo current for RSSI monitoring to be used
in SFF8472 compliant modules.
The low noise characteristics makes it suitable for STM4/OC12 applications, but also for
FTTx applications.
2. Features
s Low equivalent input noise current, typically 67 nA (RMS)
s Wide dynamic range, typically 0.85 µA to 1.5 mA (p-p)
s Differential transimpedance of 14 kΩ (typical)
s Bandwidth from DC to 650 MHz (typical)
s Differential outputs
s On-chip AGC with possibility of external control
s Single supply voltage 3.3 V, range 2.9 V to 3.6 V
s Bias voltage for PIN diode
s Current output of average photo current for RSSI monitoring
s Identical ports available on both sides of die for easy bond layout and RF polarity
selection
3. Applications
s Digital fiber optic receiver modules in telecommunications transmission systems, in
high speed data networks or in FTTx systems
4. Ordering information
Table 1: Ordering information
Type number
Package
Name
Description
TZA3026U
-
bare die, dimensions approximately
0.82 mm × 1.3 mm
Version
-
1 page  
Philips Semiconductors
TZA3026
www.DataSheet4U.com
SDH/SONET STM4/OC12 transimpedance amplifier
The parasitic capacitance can be minimized through:
1. Reducing the capacitance of the PIN diode. This is achieved by proper choice of PIN
diode and typically a high reverse voltage.
2. Reducing the parasitics around the input pad. This is achieved by placing the PIN
diode as close as possible to the TIA.
The PIN diode can be biased with a positive or a negative voltage. Figure 3 shows the PIN
diode biased positively, using the on-chip bias pad DREF. The voltage at DREF is derived
from VCC by a low-pass filter comprising internal resistor RDREF and external capacitor C2
which decouples any supply voltage noise. The value of external capacitor C2 affects the
value of PSRR and should have a minimum value of 470 pF. Increasing this value
improves the value of PSRR. The current through RDREF is measured and sourced at pad
IDREF_MON, see Section 7.3.
If the biasing for the PIN diode is done external to the IC, pad DREF can be left
unconnected. If a negative bias voltage is used, the configuration shown in Figure 4 can
be used. In this configuration, the direction of the signal current is reversed to that shown
in Figure 3. It is essential that in these applications, the PIN diode bias voltage is filtered to
achieve the best sensitivity.
For maximum freedom on bonding location, 2 outputs are available for DREF (pads 1
and 3). These are internally connected. Both outputs can be used if necessary. If only one
is used, the other can be left open.
C2
470 pF
VCC
DREF 1 or 3 RDREF
IPD 300 Ω
4 or 17
IPHOTO 2
TZA3026
001aac619
Fig 3. The PIN diode connected between
the input and pad DREF
VCC
DREF 1 or 3 RDREF
300 Ω
4 or 17
IPHOTO 2
IPD
negative
bias voltage
TZA3026
001aac620
Fig 4. The PIN diode connected between
the input and a negative supply
voltage
9397 750 14763
Product data sheet
Rev. 01 — 2 May 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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NETWORK ANALYZER
DC-IN
PATTERN
GENERATOR DATA
CLOCK
S-PARAMETER TEST SET
PORT1
PORT2
ZO = 50 Ω
ZO = 50 Ω
VCC
22 nF
55 Ω
8.2
kΩ
330 Ω
R
4 or 17
OUT
8 or 14
22 nF
TZA3026
IPHOTO
2
OUTQ 22 nF
7 or 13
9, 10, 11, 12
GND
SAMPLING OSCILLOSCOPE
12
ZO = 50 Ω
TRIGGER
INPUT
001aac626
Total impedance of the test circuit (ZT) is calculated by the equation ZT = s21 × (R + ZIN) × 2, where s21 is the insertion loss of ports 1 and 2.
Typical values: R = 330 Ω, ZIN = 75 Ω.
Fig 9. Test circuit
11 Page | ||
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