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PDF LP3971 Data sheet ( Hoja de datos )
| Número de pieza | LP3971 | |
| Descripción | POWER MANAGEMENT UNIT | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LP3971 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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January 2006
LP3971
Power Management Unit for Advanced Application
Processors
General Description
The LP3971 is a multi-function, programmable Power Man-
agement Unit, designed especially for advanced application
processors. The LP3971 is optimized for low power hand-
held applications and provides 6 low dropout, low noise
linear regulators, three DC/DC magnetic buck regulators, a
back-up battery charger and two GPIO’s. A high speed serial
interface is included to program individual regulator output
www.DataSvhoeltaegt4eUs.caosmwell as on/off control.
Key Specifications
Buck Regulators
n Programmable VOUT from 0.8 to 3.3V
n Up to 95% efficiency
n Up to 1.6A output current
n ±3% output voltage accuracy
LDO’s
n Programmable VOUT of 1.0V–3.3V
n ±3% output voltage accuracy
n 150/300/370 mA output currents
— LDO RTC 30 mA
— LDO 1 300 mA
— LDO 2 150 mA
— LDO 3 150 mA
— LDO 4 150 mA
— LDO 5 370 mA
n 100 mV (typ) dropout
Features
n Compatible with advanced applications processors
requiring DVM (Dynamic Voltage Management)
n Three buck regulators for powering high current
processor functions or I/O’s
n 6 LDO’s for powering RTC, peripherals, and I/O’s
n Backup battery charger with automatic switch for
lithium-manganese coin cell batteries and Super
capacitors
n I2C compatible high speed serial interface
n Software control of regulator functions and settings
n Precision internal reference
n Thermal overload protection
n Current overload protection
n Tiny 40-pin 5x5 mm LLP package
Applications
n PDA phones
n Smart phones
n Personal Media Players
n Digital cameras
n Application processors
— Intel Xscale
— Freescale
— Samsung
© 2006 National Semiconductor Corporation DS201807
www.national.com
1 page  
Applications Schematic Diagrams
Diagram 1 LDO 4 and LDO5 Connected To VBATTERY
www.DataSheet4U.com
See Application Hints for recommended external components and component selection
20180706
** NOTE: RTC LDO – In applications when Vbatt drops below 1.7V (ie. removing the main battery), system reset will be enabled. To void this situation, replace the
RTC LDO (pin 16) 1.0uF capacitor with a 10uF capacitor.
5 www.national.com
5 Page 
I2C Compatible Serial Interface Electrical Specifications (SDA and SCL)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 2, 6) and (Note 9)
Symbol
Parameter
VIL Low Level Input Voltage
VIH High Level Input Voltage
VOL Low Level Output Voltage
IOL Low Level Output Current
FCLK
Clock Frequency
tBF Bus-Free Time Between Start and Stop
tHOLD
Hold Time Repeated Start Condition
tCLKLP
CLK Low Period
tCLKHP
CLK High Period
tSU Set Up Time Repeated Start Condition
tDATAHLD Data Hold Time
wwtwC.LDKaSUtaSheeDta4tUa.cSoemt Up Time
TSU Set Up Time for Start Condition
TTRANS Maximum Pulse Width of Spikes that
Must be Suppressed by the Input Filter
of Both DATA & CLK Signals
Conditions
(Note 14)
(Note 14)
(Note 14)
VOL = 0.4V (Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
Min
Typ
Max
Units
−0.5
0.7 VRTC
0
3.0
0.3 VRTC
VRTC
0.2 VTRC
V
mA
400 kHz
1.3 µs
0.6 µs
1.3 µs
0.6 µs
0.6 µs
0 µs
100 ns
0.6 µs
50 ns
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
Note 4: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board
is 50 mm x 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22˚C, still air. Power
dissipation is 1W. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation
exists, special care must be paid to thermal dissipation issues in board design. The value of θJA of this product can vary significantly, depending on PCB material,
layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal
dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and
Power Dissipation section of this datasheet.
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7). The machine model is a 200 pF
capacitor discharged directly into each pin. (EAIJ)
Note 6: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are production
tested, guaranteed through statistical analysis or guaranteed by design. All limits at temperature extremes are guaranteed via correlation using standard Statistical
Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Note 7: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
Note 8: Back-up battery charging current is programmable via the I2C compatible interface. Refer to the Application Section for more information.
Note 9: The I2C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kΩ to 20 kΩ range.
Note 10: LDO_RTC voltage can track LDO1 (I/O) Voltage. Refer to LP3971 Controls Section for more information.
Note 11: VIN minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages below the minimum
input operating voltage.
Note 12: The input voltage range recommended for ideal applications performance for the specified output voltages is given below:
VIN = 2.7V to 5.5V for 0.80V < VOUT < 1.8V
VIN = (VOUT+ 1V) to 5.5V for 1.8V ≤ VOUT ≤ 3.3V
Note 13: Test condition: for VOUT less than 2.7V, VIN = 3.6V; for VOUT greater than or equal to 2.7V, VIN = VOUT+ 1V.
Note 14: This electrical specification is guaranteed by design.
Note 15: An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 16: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply
for input voltages below 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5.
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LP3971.PDF ] | |
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