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PDF LM5115 Data sheet ( Hoja de datos )
| Número de pieza | LM5115 | |
| Descripción | Secondary Side Post Regulator Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LM5115 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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PRELIMINARY
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LM5115
Secondary Side Post Regulator Controller
General Description
The LM5115 controller contains all of the features necessary
to implement multiple output power converters utilizing the
Secondary Side Post Regulation (SSPR) technique. The
SSPR technique develops a highly efficient and well regu-
lated auxiliary output from the secondary side switching
waveform of an isolated power converter. Regulation of the
auxiliary output voltage is achieved by leading edge pulse
width modulation (PWM) of the main channel duty cycle.
Leading edge modulation is compatible with either current
mode or voltage mode control of the main output. The
LM5115 drives external high side and low side NMOS power
switches configured as a synchronous buck regulator. A
current sense amplifier provides overload protection and
operates over a wide common mode input range. Additional
features include a low dropout (LDO) bias regulator, error
amplifier, precision reference, adaptive dead time control of
the gate signals and thermal shutdown.
Features
n Self-synchronization to main channel output
n Free-run mode for buck regulation of DC input
n Leading edge pulse width modulation
n Voltage-mode control with current injection and input line
feed-forward
n Operates from AC or DC input up to 75V
n Wide 4.5V to 30V bias supply range
n Wide 0.75V to 12V output range.
n Top and bottom gate drivers sink 2.5A peak
n Adaptive gate driver dead-time control
n Wide bandwidth error amplifier (4MHz)
n Programmable soft-start
n Thermal shutdown protection
n TSSOP-16 or thermally enhanced LLP-16 packages
Typical Application Circuit
20134901
FIGURE 1. Simplified Multiple Output Power Converter Utilizing SSPR Technique
© 2005 National Semiconductor Corporation DS201349
www.national.com
1 page  
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VBIAS to GND
VCC to GND
HS to GND
OUT, CS to GND
All other inputs to GND
Storage Temperature Range
Junction Temperature
–0.3V to 32V
–0.3V to 9V
–1V to 80V
– 0.3V to 12V
−0.3V to 7.0V
–55˚C to +150˚C
+150˚C
ESD Rating
HBM (Note 2)
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Operating Ratings
VBIAS supply voltage
VCC supply voltage
HS voltage
HB voltage
Operating Junction Temperature
5V to 30V
5V to 7.5V
0V to 75V
VCC + HS
–40˚C to +125˚C
PARAMETER
Supply Voltage, VBIAS
Supply Voltage, VCC
Supply voltage bypass, CVBIAS
Reference bypass capacitor, CVCC
HB-HS bootstrap capacitor
SYNC Current Range (VCC = 4.5V)
RAMP Saw Tooth Amplitude
VOUT regulation voltage
Typical Operating Conditions
MIN
4.5
4.5
0.1
0.1
0.047
50
1
0.75
TYP
1
1
MAX
30
7
10
150
1.75
12
UNITS
V
V
µF
µF
µF
µA
V
V
Electrical Characteristics Unless otherwise specified, TJ = –40˚C to +125˚C, VBIAS = 12V, No Load on
LO or HO.
SYMBOL
PARAMETER
CONDITIONS
VBIAS SUPPLY
Ibias VBIAS Supply Current
VCC LOW DROPOUT BIAS REGULATOR
FSYNC = 200kHz
VccReg VCC Regulation
VCC open circuit. Outputs not
switching
VCC Current Limit
(Note 4)
VCC Under-voltage Lockout Voltage Positive going VCC
VCC Under-voltage Hysteresis
SOFT-START
SS Source Impedance
SS Discharge Impedance
ERROR AMPLIFIER and FEEDBACK REFERENCE
VREF FB Reference Voltage
Measured at FB pin
FB Input Bias Current
FB = 2V
COMP Source Current
Open Loop Voltage Gain
GBW Gain Bandwidth Product
Vio Input Offset Voltage
COMP Offset
Threshold for VHO = high RAMP = CS
= VOUT = 0V
RAMP Offset
Threshold for VHO = high COMP =
1.5V, CS = VOUT = 0V
CURRENT SENSE AMPLIFIER
Current Sense Amplifier Gain
Output DC Offset
Amplifier Bandwidth
MIN
6.65
4
0.2
43
0.737
-7
TYP
7
40
0.25
60
100
0.75
0.2
300
60
4
0
2
1.1
16
1.27
500
MAX
4
7.15
4.5
0.3
77
0.763
0.5
7
UNITS
mA
V
mA
V
V
kΩ
Ω
V
µA
µA
dB
MHz
mV
V
V
V/V
V
kHz
5 www.national.com
5 Page 
Error Amplifier and Soft-Start (FB,
CO, & COMP, SS) (Continued)
fier is configured as an open drain output it can be disabled
by connecting FB to ground. The current sense amplifier and
current limiting function will be described in a later section.
Leading Edge Pulse Width
Modulation
Unlike conventional voltage mode controllers, the LM5115
implements leading edge pulse width modulation. A current
source equal to 3 times the ISYNC current is used to charge
the capacitor connected to the RAMP pin as shown in Figure
4. The ramp signal and the output of thewwewrro.Dr aatmaSphliefieert4U.com
(COMP) are combined through a resistor network to produce
a voltage ramp with variable dc offset (CRMIX in Figure 4).
The high side MOSFET which drives the HS pin is held in the
off state at the beginning of the phase signal. When the
voltage of CRMIX exceeds the internal threshold voltage CV,
the PWM comparator turns on the high side MOSFET. The
HS pin rises and the MOSFET delivers current from the main
converter phase signal to the output of the auxiliary regula-
tor. The PWM cycle ends when the phase signal falls and
power is no longer supplied to the drain of the high side
MOSFET.
FIGURE 4. Synchronization and Leading Edge Modulation
20134914
Leading edge modulation of the auxiliary PWM controller is
required if the main converter is implemented with peak
current mode control. If trailing edge modulation were used,
the additional load on the transformer secondary from the
auxiliary channel would be drawn only during the first portion
of the phase signal pulse. Referring to Figure 5, the turn off
the high side MOSFET of the auxiliary regulator would cre-
ate a non-monotonic negative step in the transformer cur-
rent. This negative current step would produce instability in a
peak current mode controller. With leading edge modulation,
the additional load presented by the auxiliary regulator on
the transformer secondary will be present during the latter
portion of the phase signal. This positive step in the phase
signal current can be accommodated by a peak current
mode controller without instability.
FIGURE 5. Leading versus Trailing Edge Modulation
11
20134920
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet LM5115.PDF ] | |
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