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PDF CY7C68000A Data sheet ( Hoja de datos )
| Número de pieza | CY7C68000A | |
| Descripción | MoBL-USB TX2 USB 2.0 UTMI Transceiver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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wwwC.DYat7aSChe6e8t40U.0co0mA
MoBL-USB™ TX2 USB 2.0 UTMI
Transceiver
MoBL-USB™ TX2 Features
■ UTMI-compliant and USB 2.0 certified for device operation
■ Operates in both USB 2.0 High Speed (HS), 480 Mbits/second,
and Full Speed (FS), 12 Mbits/second
■ Optimized for Seamless Interface with Intel® Monahans Appli-
cations Processors
■ Tri-state Mode enables sharing of UTMI Bus with other devices
■ Serial-to-Parallel and Parallel-to-Serial Conversions
■ 8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional
External Data Interface
■ Synchronous Field and EOP Detection on Receive Packets
■ Synchronous Field and EOP Generation on Transmit Packets
■ Data and Clock Recovery from the USB Serial Stream
■ Bit stuffing and unstuffing; Bit Stuff Error Detection
■ Staging Register to manage Data Rate variation due to Bit
stuffing and unstuffing
■ 16-bit 30 MHz and 8-bit 60 MHz Parallel Interface
■ Ability to switch between FS and HS terminations and signaling
■ Supports detection of USB Reset, Suspend, and Resume
■ Supports HS identification and detection as defined by the USB
2.0 Specification
Logic Block Diagram
■ Supports transmission of Resume Signaling
■ 3.3V Operation
■ Two package options: 56-pin QFN and 56-pin VFBGA
■ All required terminations, including 1.5 Kohm pull up on
DPLUS, are internal to chip
■ Supports USB 2.0 Test Modes
The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB)
specification revision 2.0 transceiver, serial and deserializer, to a
parallel interface of either 16 bits at 30 MHz or eight bits at 60
MHz. The MoBL-USB TX2 provides a high speed physical layer
interface that operates at the maximum allowable USB 2.0
bandwidth. This enables the system designer to keep the
complex high speed analog USB components external to the
digital ASIC. This decreases development time and associated
risk. A standard USB 2.0-certified interface is provided and is
compliant with Transceiver Macrocell Interface (UTMI) specifi-
cation version 1.05 dated 3/29/2001.
This product is also optimized to seamlessly interface with
Monahans -P & -L applications processors. It has been charac-
terized by Intel and is recommended as the USB 2.0 UTMI trans-
ceiver of choice for its Monahans processors. It is also capable
of tri-stating the UTMI bus, while suspended, to enable the bus
to be shared with other devices.
Two packages are defined for the family: 56-pin QFN and 56-pin
VFBGA.
The functional block diagram follows.
Tri_state
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-08052 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 5, 2008
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Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment
1234567
8
A 1A 2A 3A 4A 5A 6A 7A 8A
B 1B 2B 3B 4B 5B 6B 7B 8B
C 1C 2C 3C 4C 5C 6C 7C 8C
D 1D 2D
7D 8D
E 1E 2E
7E 8E
F 1F 2F 3F 4F 5F 6F 7F 8F
G 1G 2G 3G 4G 5G 6G 7G 8G
H 1H 2H 3H 4H 5H 6H 7H 8H
Document #: 38-08052 Rev. *G
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HS/FS Interface Timing - 30 MHz
Figure 4. 30 MHz Timing Interface Timing Constraints
wwwC.DYat7aSChe6et84U0.c0o0mA
CLK
Control_In
DataIn
Control_Out
DataOut
TCSU_MIN
TCH_MIN
TDSU_MIN
TDH_MIN
TVSU_MIN
TVH_MIN
TCDO
TCCO
TCVO
Table 4. 30 MHz Timing Interface Timing Constraints Parameters
Parameter
TCSU_MIN
TCH_MIN
TDSU_MIN
TDH_MIN
TCCO
TCDO
TVSU_MIN
TVH_MIN
TCVO
Description
Minimum setup time for TXValid
Minimum hold time for TXValid
Minimum setup time for Data (Transmit direction)
Minimum hold time for Data (Transmit direction)
Clock to Control Out time for TXReady, RXValid,
RXActive and RXError
Clock to Data out time (Receive direction)
Minimum setup time for ValidH (transmit Direction)
Minimum hold time for ValidH (Transmit direction)
Clock to ValidH out time (Receive direction)
Min
16
1
16
1
1
1
16
1
1
Typ
Suspend
Figure 5. Tri-state Mode Timing Constraints
Ttssu Ttspd
Tri-state
Output / IO
XXXX
Hi-Z
Max Unit
ns
ns
ns
ns
20 ns
20 ns
ns
ns
20 ns
Ttspd
Notes
Table 5. Tri-state Mode Timing Constraints Parameters
Parameter
Ttssu
Ttspd
Description
Minimum setup time for Tri-state
Propagation Delay for Tri-State mode
Document #: 38-08052 Rev. *G
Min Typ Max Unit Notes
0 ns
50 ns
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| PDF Descargar | [ Datasheet CY7C68000A.PDF ] | |
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