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PDF LTC3413 Data sheet ( Hoja de datos )
| Número de pieza | LTC3413 | |
| Descripción | 3A/ 2MHz Monolithic Synchronous Regulator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC3413www.DataSheet4U.com
3A, 2MHz Monolithic
Synchronous Regulator for
DDR/QDR Memory Termination
FEATURES
s High Efficiency: Up to 90%
s ±3A Output Current
s Symmetrical Source and Sink Output Current Limit
s Low RDS(ON) Internal Switch: 85mΩ
s No Schottky Diode Required
s 2.25V to 5.5V Input Voltage Range
s VOUT = VREF/2
s ±1% Output Voltage Accuracy
s Programmable Switching Frequency: Up to 2MHz
s Power Good Output Voltage Monitor
s Overtemperature Protected
s Available in 16-Lead TSSOP Exposed Pad Package
U
APPLICATIO S
s Bus Termination: DDR and QDRTM Memory,
SSTL, HSTL, ...
s Notebook Computers
s Distributed Power Systems
DESCRIPTIO
The LTC®3413 is a high efficiency monolithic synchro-
nous step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage equal to (0.5)VREF while sourcing
or sinking up to 3A of output current. An internal voltage
divider reduces component count and eliminates the need
for external resistors by dividing the reference voltage in
half. The internal synchronous power switch with 85mΩ
on-resistance increases efficiency and eliminates the need
for an external Schottky diode. Switching frequencies up
to 2MHz are set by an external resistor.
Forced-continuous operation in the LTC3413 reduces
noise and RF interference. Fault protection is provided by
an overcurrent comparator that limits output current dur-
ing both sourcing and sinking operations. Adjustable
compensation allows the transient response to be opti-
mized over a wide range of loads and output capacitors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
TYPICAL APPLICATIO
VIN
2.5V
22µF
4.7M
330pF
5.11k
2200pF
SVIN PVIN
PGOOD
VREF
SW
LTC3413
RUN/SS PGND
SGND
ITH
RT
VFB
L1
0.47µH
COUT
100µF
×2
VOUT
1.25V
±3A
309k
3413 F01a
L1: VISHAY DALE IHLP-2525CZ-01 0.47
COUT: TDK C4532X5R0J107M
Figure 1a. High Efficiency Bus Termination Supply
100
90
VIN = 2.5V
f = 1MHz
80
70
60
50
40
30
20
10
0
0.01 0.1
1
LOAD CURRENT (A)
10
3413 F01b
Figure 1b. Efficiency vs Load Current
sn3413 3413fs
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LTC3413www.DataSheet4U.com
PI FU CTIO S
SVIN (Pin 1): Signal Input Supply. Decouple this pin to
SGND with a capacitor. SVIN must be greater or equal to
PVIN, however, the difference between SVIN and PVIN must
be less than 0.5V.
PGOOD (Pin 2): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage is
not within ±10% of regulation point.
ITH (Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V to
1.4V with 0.6V corresponding to the zero-sense voltage
(zero current).
VFB (Pin 4): Feedback Pin. Receives the feedback voltage
from the output.
RT (Pin 5): Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
VREF (Pin 6): Reference Voltage Input. The positive input
of the internal error amplifier senses one-half of the
voltage at this pin through a resistor divider.
RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3413. In shutdown
all functions are disabled drawing < 1µA of supply current.
A capacitor to ground from this pin sets the ramp time to
full output current.
SGND (Pin 8): Signal Ground. All small-signal compo-
nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
PVIN (Pins 9, 16): Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 10, 11, 14, 15): Switch Node Connection to
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
PGND (Pins 12, 13): Power Ground. Connect this pin
closely to the (–) terminal of CIN and COUT.
EXPOSED PAD (Pin 17): Should be connected to SGND.
W
FU CTIO AL DIAGRA
SVIN
1
VREF
6
SGND
8
SVIN
VFB
4
0.9VREF
2
+
–
ERROR
AMPLIFIER
+
–
+
PGOOD
2
1.1VREF
2
–
ITH
3
SLOPE
COMPENSATION
RECOVERY
PMOS CURRENT
COMPARATOR
+
–
OSCILLATOR
SLOPE
COMPENSATION
LOGIC
–
+
RUN NMOS CURRENT
COMPARATOR
57
RT RUN/SS
PVIN PVIN
9 16
10 SW
11 SW
14 SW
15 SW
12 PGND
13 PGND
3413 BD
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LTC3413www.DataSheet4U.com
APPLICATIO S I FOR ATIO
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (RDS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components and output capaci-
tor shown in Figure 1a will provide adequate compensa-
tion for most applications.
Output Voltage Tracking of VREF
For applications in which the VREF pin is connected to the
VIN pin, the output voltage will be equal to one-half of the
voltage on the VIN pin. Because the output voltage will
track the input voltage, any disturbance on VIN will appear
on VOUT. For example, a load step transient could cause
the input voltage to drop if there is insufficient bulk
capacitance at the VIN pin. The corresponding drop in the
output voltage during the load step transient is caused by
the VOUT tracking of VIN and should not be confused with
poor load regulation.
Design Example
As a design example, consider using the LTC3413 in an
application with the following specifications: VIN = 2.5V,
VOUT = 1.25V, IOUT(MAX) = ±3A, f = 1MHz.
First, calculate the timing resistor:
ROSC
=
3.23 •1011
1• 106
–
10kΩ
=
313kΩ
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current:
L
=
1.25V
1MHz •1.2A
1–
1.25V
2.5V
=
0.47µH
Using a 0.47µH inductor results in a maximum ripple
current of:
∆IL
=
1.25V
1MHz • 0.47µH
1–
1.25V
2.5V
=
1.33A
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100µF ceramic capacitors will be used. CIN should be sized
for a maximum current rating of:
IRMS
=
3A
1.25V
2.5V
2.5V
1.25V
–
1
=
1.5ARMS
Decoupling the PVIN pins with two 100µF capacitors is
sn3413 3413fs
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC3413.PDF ] | |
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