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PDF MAX9218 Data sheet ( Hoja de datos )
| Número de pieza | MAX9218 | |
| Descripción | DC-Balanced LVDS Deserializer | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX9218 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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19-3557; Rev 1; 4/05
www.DataSheet4U.com
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
General Description
The MAX9218 digital video serial-to-parallel converter
deserializes a total of 27 bits during data and control
phases. In the data phase, the LVDS serial input is con-
verted to 18 bits of parallel video data and in the control
phase, the input is converted to 9 bits of parallel control
data. The separate video and control phases take
advantage of video timing to reduce the serial data rate.
The MAX9218 pairs with the MAX9217 serializer to form
a complete digital video transmission system.
Proprietary data decoding reduces EMI and provides
DC balance. The DC balance allows AC-coupling, pro-
viding isolation between the transmitting and receiving
ends of the interface. The MAX9218 features a selec-
table rising or falling output latch edge.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9218 operates from a +3.3V core supply and
features a separate output supply for interfacing to 1.8V
to 3.3V logic-level inputs. This device is available in 48-
lead Thin QFN and TQFP packages and is specified
from -40°C to +85°C.
Applications
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
TOP VIEW
Features
♦ Proprietary Data Decoding for DC Balance and
Reduced EMI
♦ Control Data Deserialized During Video Blanking
♦ Five Control Data Inputs Are Single Bit-Error
Tolerant
♦ Output Transition Time Is Scaled to Operating
Frequency for Reduced EMI
♦ Staggered Output Switching Reduces EMI
♦ Output Enable Allows Busing of Outputs
♦ Clock Pulse Stretch on Lock
♦ Wide ±2% Reference Clock Tolerance
♦ Synchronizes to MAX9217 Serializer Without
External Control
♦ ISO 10605 ESD Protection
♦ Separate Output Supply Allows Interface to 1.8V
to 3.3V Logic
♦ +3.3V Core Power Supply
♦ Space-Saving Thin QFN and TQFP Packages
♦ -40°C to +85°C Operating Temperature
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
PKG
CODE
MAX9218ECM -40°C to +85°C 48 TQFP
C48-5
MAX9218ETM -40°C to +85°C 48 Thin QFN-EP* T4866-1
*EP = Exposed pad.
Pin Configurations
R/F
RNG1
VCCLVDS
IN+
IN-
LVDS GND
PLL GND
VCCPLL
RNG0
GND
VCC
REFCLK
1
2
3
4
5
6
7
8
9
10
11
12
MAX9218
36 RGB_OUT7
35 RGB_OUT6
34 RGB_OUT5
33 RGB_OUT4
32 RGB_OUT3
31 RGB_OUT2
30 RGB_OUT1
29 RGB_OUT0
28 PCLK_OUT
27 LOCK
26 VCCO
25 VCCOGND
R/F
RNG1
VCCLVDS
IN+
IN-
LVDS GND
PLL GND
VCCPLL
RNG0
GND
VCC
REFCLK
1
2
3
4
5
6
7
8
9
10
11
12
MAX9218
36 RGB_OUT7
35 RGB_OUT6
34 RGB_OUT5
33 RGB_OUT4
32 RGB_OUT3
31 RGB_OUT2
30 RGB_OUT1
29 RGB_OUT0
28 PCLK_OUT
27 LOCK
26 VCCO
25 VCCO GND
TQFP
THIN QFN-EP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
(VCC_ = +3.3V, CL = 8pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
80
70
60
50
40
30
20
10
0
3 7 11 15 19 23 27 31 35
FREQUENCY (MHz)
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
7
6
5 tR
4
3 tF
2
1
0
1.8
RNG1 = RNG0 = HIGH
2.1 2.4 2.7 3.0
OUTPUT SUPPLY VOLTAGE (V)
3.3
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
7
6 tR
5
4 tF
3
2
1
0
1.8
RNG1 = RNG0 = BOTH NOT HIGH
2.1 2.4 2.7 3.0
OUTPUT SUPPLY VOLTAGE (V)
3.3
10-14
CAT5e
BIT-ERROR RATE
vs. CABLE LENGTH
10-13
10-12
10-11
10-10
0
35MHz CLOCK
700Mbps DATA RATE
FOR <12m, BER < 10-12
4 8 12 16
CAT5e CABLE LENGTH (m)
20
_______________________________________________________________________________________ 5
5 Page 
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27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
RGB_IN
CNTL_IN
DE_IN
1
0
OUT
CMF
PCLK_IN
RNG0
RNG1
PWRDWN
PLL
TIMING AND
CONTROL
MOD0
MOD1
MAX9217
VCC
130Ω
*
*
82Ω
130Ω
IN
82Ω
1
0
RNG0
RNG1
PLL
TIMING AND
CONTROL
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
*CAPS CAN BE AT EITHER END.
Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link
R/F
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
PCLK_OUT
REF_IN
PWRDWN
LOCK
RGB_IN
CNTL_IN
DE_IN
1
0
OUT
CMF
PCLK_IN
RNG0
RNG1
PWRDWN
PLL
TIMING AND
CONTROL
MAX9217
MOD0
MOD1
VCC
130Ω
130Ω
IN
82Ω 82Ω
1
0
RNG0
RNG1
PLL
TIMING AND
CONTROL
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
R/F
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
PCLK_OUT
REF_IN
PWRDWN
LOCK
Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX9218.PDF ] | |
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