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PDF MAX9217 Data sheet ( Hoja de datos )
| Número de pieza | MAX9217 | |
| Descripción | DC-Balanced LVDS Serializer | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX9217 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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19-3558; Rev 2; 10/05
www.DataSheet4U.com
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
General Description
The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reduc-
ing the serial data rate. The data enable input determines
when the video or control data is serialized.
The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PC board traces or twisted-
pair cable. Proprietary data encoding reduces EMI and
provides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiv-
ing ends of the interface. The LVDS output is internally
terminated with 100Ω.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9217 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in 48-lead
Thin QFN and TQFP packages and is specified from
-40°C to +85°C.
Applications
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
Features
o Proprietary Data Encoding for DC Balance and
Reduced EMI
o Control Data Sent During Video Blanking
o Five Control Data Inputs Are Single-Bit-Error
Tolerant
o Programmable Phase-Shifted LVDS Signaling
Reduces EMI
o Output Common-Mode Filter Reduces EMI
o Greater than 10m STP Cable Drive
o Wide ±2% Reference Clock Tolerance
o ISO 10605 ESD Protection
o Separate Input Supply Allows Interface to 1.8V to
3.3V Logic
o +3.3V Core Supply
o Space-Saving Thin QFN and TQFP Packages
o -40°C to +85°C Operating Temperature
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
MAX9217ECM -40°C to +85°C 48 TQFP
MAX9217ETM -40°C to +85°C 48 Thin QFN-EP*
*EP = Exposed pad.
PKG
CODE
C48-5
T4866-1
Pin Configurations
TOP VIEW
GND
VCCIN
RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
RGB_IN17
CNTL_IN0
CNTL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
MAX9217
36 RNG0
35 RNG1
34 VCCLVDS
33 OUT+
32 OUT-
31 LVDS GND
30 LVDS GND
29 CMF
28 PWRDWN
27 VCCPLL
26 PLL GND
25 MOD1
GND
VCCIN
RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
RGB_IN17
CNTL_IN0
CNTL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
MAX9217
36 RNG0
35 RNG1
34 VCCLVDS
33 OUT+
32 OUT-
31 LVDS GND
30 LVDS GND
29 CMF
28 PWRDWN
27 VCCPLL
26 PLL GND
25 MOD1
TQFP
THIN QFN-EP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
Pin Description
PIN
1, 13, 37
2
3–10,
39–48
11, 12, 15–21
14, 38
22
23
24
25
26
27
28
29
30, 31
32
33
34
35
36
EP
NAME
GND
VCCIN
FUNCTION
Input Buffer Supply and Digital Supply Ground
Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
RGB_IN[17:0] into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
CNTL_IN[8:0]
VCC
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
DE_IN
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
PCLK_IN
MOD0
MOD1
PLL GND
VCCPLL
PWRDWN
CMF
LVDS GND
OUT-
OUT+
VCCLVDS
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled
down to GND.
LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled
down to GND.
PLL Supply Ground
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
LVDS Supply Ground
Inverting LVDS Serial Data Output
Noninverting LVDS Serial Data Output
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
RNG1
RNG0
GND
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PC board GND.
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
RGB_IN
CNTL_IN
DE_IN
1
0
OUT
CMF
PCLK_IN
RNG0
RNG1
PWRDWN
PLL
TIMING AND
CONTROL
MOD0
MOD1
MAX9217
VCC
130Ω
*
*
130Ω
IN
82Ω 82Ω
1
0
RNG0
RNG1
PLL
TIMING AND
CONTROL
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
*CAPACITORS CAN BE AT EITHER END.
100Ω DIFFERENTIAL STP CABLE
Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link
R/F
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
PCLK_OUT
REF_IN
PWRDWN
LOCK
RGB_IN
CNTL_IN
DE_IN
1
0
OUT
CMF
PCLK_IN
RNG0
RNG1
PWRDWN
PLL
TIMING AND
CONTROL
MAX9217
MOD0
MOD1
VCC
130Ω
130Ω
IN
82Ω 82Ω
1
0
RNG0
RNG1
PLL
TIMING AND
CONTROL
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
R/F
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
PCLK_OUT
REF_IN
PWRDWN
LOCK
Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX9217.PDF ] | |
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