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PDF MAX9214 Data sheet ( Hoja de datos )
| Número de pieza | MAX9214 | |
| Descripción | Programmable DC-Balance 21-Bit Deserializers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2864; Rev 3; 4/04
www.DataSheet4U.com
Programmable DC-Balance
21-Bit Deserializers
General Description
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 deserialize three LVDS serial data inputs into
21 single-ended LVCMOS/LVTTL outputs. A parallel rate
LVDS clock received with the LVDS data streams pro-
vides timing for deserialization. The outputs have a sepa-
rate supply, allowing 1.8V to 5V output logic levels.
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 feature programmable DC balance, which
allows isolation between a serializer and deserializer
using AC-coupling. Each deserializer decodes data
transmitted by one of MAX9209/MAX9211/MAX9213/
MAX9215 serializers.
The MAX9210/MAX9212/MAX9214/MAX9216 have ris-
ing-edge output strobes, and when DC balance is not
programmed, are compatible with non-DC-balanced
21-bit deserializers such as the DS90CR216A and
DS90CR218A. The MAX9220/MAX9222 have falling-
edge output strobes.
Two frequency versions and two DC-balance default con-
ditions are available for maximum replacement flexibility
and compatibility with popular non-DC-balanced deserial-
izers. The transition time of the single-ended outputs is
increased on the low-frequency version parts (MAX9210/
MAX9212/MAX9220) for reduced EMI. The LVDS inputs
meet IEC 61000-4-2 Level 4 ESD specification, ±15kV for
Air Discharge and ±8kV Contact Discharge.
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 are available in TSSOP and space-saving QFN
packages, and operate over the -40°C to +85°C temper-
ature range.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Functional Diagram and Pin Configurations appear at end
of data sheet.
Features
♦ Programmable DC Balance or Non-DC Balance
♦ DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
♦ As Low as 8MHz Operation
(MAX9210/MAX9212/MAX9220)
♦ Falling-Edge Output Strobe (MAX9220/MAX9222)
♦ Slower Output Transitions for Reduced EMI
(MAX9210/MAX9212/MAX9220)
♦ High-Impedance Outputs when PWRDWN is Low
Allow Output Busing
♦ Pin Compatible with DS90CR216A/DS90CR218A
(MAX9210/MAX9212/MAX9214/MAX9216)
♦ Fail-Safe Inputs in Non-DC-Balanced Mode
♦ 5V Tolerant PWRDWN Input
♦ PLL Requires No External Components
♦ Up to 1.785Gbps Throughput
♦ Separate Output Supply Pins Allow Interface to
1.8V, 2.5V, 3.3V, and 5V Logic
♦ LVDS Inputs Meet IEC 61000-4-2 Level 4 ESD
Requirements
♦ LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS
Standard
♦ Low-Profile 48-Lead TSSOP and Space-Saving
QFN Packages
♦ +3.3V Main Power Supply
♦ -40°C to +85°C Operating Temperature Range
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX9210ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9210EUM
-40°C to +85°C 48 TSSOP
MAX9212ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9212EUM* -40°C to +85°C 48 TSSOP
MAX9214ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9214EUM
-40°C to +85°C 48 TSSOP
MAX9216ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9216EUM* -40°C to +85°C 48 TSSOP
MAX9220ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9220EUM
-40°C to +85°C 48 TSSOP
MAX9222ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9222EUM
-40°C to +85°C 48 TSSOP
*Future product—contact factory for availability.
**EP = Exposed pad.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Programmable DC-Balance
21-Bit Deserializers
Typical Operating Characteristics
(VCC = VCCO = +3.3V, CL = 8pF, PWRDWN = high, differential input voltage VID = 0.2V, input common-mode voltage VCM = 1.2V,
TA = +25°C, unless otherwise noted.)
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
100
MAX9220
90 DC-BALANCED MODE
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
100
MAX9220
90 NON-DC-BALANCED MODE
80
WORST-CASE PATTERN
70
60
80
70 WORST-CASE PATTERN
60
50
40
30
20
5
27 - 1 PRBS
10 15 20 25 30 35 40
FREQUENCY (MHz)
50
40
30
20
5
27 - 1 PRBS
10 15 20 25 30 35 40
FREQUENCY (MHz)
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
160
MAX9214
DC-BALANCED MODE
140
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
160
MAX9214
NON-DC-BALANCED MODE
140
120 120
100 100
80 80
60 60
40
5
20 35 50 65
FREQUENCY (MHz)
80
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
5
MAX9214
4
tR
3
tF
2
40
15
30 45 60 75
FREQUENCY (MHz)
90
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
7
MAX9220
6
tR
5
4
tF
3
2
1
2.5
3.0 3.5 4.0 4.5
OUTPUT SUPPLY VOLTAGE (V)
5.0
1
2.5
3.0 3.5 4.0 4.5
OUTPUT SUPPLY VOLTAGE (V)
5.0
_______________________________________________________________________________________ 5
5 Page 
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Programmable DC-Balance
21-Bit Deserializers
MAX9209
MAX9211
MAX9213
MAX9215
7
(7 + 2):1
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
SERIALIZER INSTEAD OF THE DESERIALIZER.
TxOUT
RxIN
100Ω
MAX9210
MAX9212
MAX9214
MAX9216
MAX9220
MAX9222
1:(9 - 2)
7
7
TxIN
(7 + 2):1
100Ω
1:(9 - 2)
7
RxOUT
7
(7 + 2):1
100Ω
1:(9 - 2)
7
PWRDWN
TxCLK IN
PLL
21:3 SERIALIZER
TxCLK OUT
100Ω
RxCLK IN
PLL
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (RT), the LVDS driver
output resistor (RO), and the series AC-coupling capac-
itors (C). The RC time constant for two equal-value
series capacitors is (C x (RT + RO))/2 (Figure 12). The
RC time constant for four equal-value series capacitors
is (C x (RT + RO))/4 (Figure 13).
RT is required to match the transmission line imped-
ance (usually 100Ω) and RO is determined by the LVDS
driver design (the minimum differential output resis-
tance of 78Ω for the MAX9209/MAX9211/MAX9213/
MAX9215 serializers is used in the following example).
This leaves the capacitor selection to change the sys-
tem time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1)
where:
C = AC-coupling capacitor (F).
tB = bit time (s).
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
RT = termination resistor (Ω).
RO = output resistance (Ω).
Equation 1 is for two series capacitors (Figure 12). The
bit time (tB) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 13).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO))
C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.0773µF
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX9214.PDF ] | |
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