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PDF LTC1749 Data sheet ( Hoja de datos )
| Número de pieza | LTC1749 | |
| Descripción | 12-Bit 80Msps Wide Bandwidth ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Sample Rate: 80Msps
s PGA Front End (2.25VP-P or 1.35VP-P Input Range)
s 71.8dB SNR and 87dB SFDR (PGA = 0)
s 70.2dB SNR and 87dB SFDR (PGA = 1)
s 500MHz Full Power Bandwidth S/H
s No Missing Codes
s Single 5V Supply
s Power Dissipation: 1.45W
s Two Pin Selectable Reference Values
s Data Ready Output Clock
s Pin Compatible 14-Bit 80Msps Device (LTC1750)
s 48-Pin TSSOP Package
U
APPLICATIO S
s Direct IF Sampling
s Telecommunications
s Receivers
s Cellular Base Stations
s Spectrum Analysis
s Communications Test Equipment
s Undersampling
LTC1749www.DataSheet4U.com
12-Bit, 80Msps
Wide Bandwidth ADC
DESCRIPTIO
The LTC®1749 is an 80Msps, 12-bit A/D converter de-
signed for digitizing wide dynamic range signals up to
frequencies of 500MHz. The input range of the ADC can be
optimized with the on-chip PGA sample-and-hold circuit
and flexible reference circuitry.
The LTC1749 has a highly linear sample-and-hold circuit
with a bandwidth of 500MHz. The SFDR is 80dB with an
input frequency of 250MHz. Ultralow jitter of 0.15psRMS
allows undersampling of IF frequencies with minimal
degradation in SNR. DC specs include ±1LSB INL and no
missing codes.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to low voltage
DSPs or FIFOs.
The 48-pin TSSOP package with a flow-through pinout
simplifies the board layout.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
PGA
AIN+
±1.125V
DIFFERENTIAL
ANALOG INPUT AIN–
SENSE
RANGE
SELECT
VCM
4.7µF
2VREF
80Msps, 12-Bit ADC with a 2.25V Differential Input Range
S/H
CIRCUIT
12-BIT
PIPELINED ADC
BUFFER
DIFF AMP
CORRECTION
LOGIC AND
12
OUTPUT
SHIFT
LATCHES
REGISTER
OVDD
0.1µF
•••
D11
D0
CLKOUT
OGND
VDD
1µF
1µF
0.5V TO 5V
0.1µF
5V
1µF
CONTROL LOGIC
GND
REFLB
0.1µF
1µF
REFHA
4.7µF
REFLA REFHB
ENC ENC MSBINV
0.1µF
1µF
DIFFERENTIAL
ENCODE INPUT
1749 BD
1749f
1
1 page  
LTC1749www.DataSheet4U.com
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 80MHz, differential ENC/ENC = 2VP-P 80MHz
sine wave, input range = ±1.125V differential, unless otherwise specified.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
TYPICAL PERFOR A CE CHARACTERISTICS
INL
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
1749 G01
8192 Point FFT, fIN = 15MHz,
–10dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
1749 G04
DNL
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
1749 G02
8192 Point FFT, fIN = 15MHz,
–20dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
1749 G05
8192 Point FFT, fIN = 15MHz,
–1dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
1749 G03
8192 Point FFT, fIN = 30.2MHz,
–1dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
1749 G06
1749f
5
5 Page 
LTC1749www.DataSheet4U.com
APPLICATIO S I FOR ATIO
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π) • FIN • TJITTER
CONVERTER OPERATION
The LTC1749 is a CMOS pipelined multistep converter with
a front-end PGA. The converter has four pipelined ADC
stages; a sampled analog input will result in a digitized value
five cycles later, see the Timing Diagram section. The analog
input is differential for improved common mode noise
immunity and to maximize the input range. Additionally,
the differential input drive will reduce even order harmon-
ics of the sample-and-hold circuit. The encode input is also
differential for improved common mode noise immunity.
The LTC1749 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
PGA
AIN+
INPUT
AIN– S/H
FIRST PIPELINED
ADC STAGE
(5 BITS)
SECOND PIPELINED
ADC STAGE
(4 BITS)
THIRD PIPELINED
ADC STAGE
(4 BITS)
FOURTH PIPELINED
ADC STAGE
(2 BITS)
VCM
4.7µF
2.0V
REFERENCE
RANGE
SELECT
SHIFT REGISTER
AND CORRECTION
SENSE
REF
BUF
REFL
REFH INTERNAL CLOCK SIGNALS
DIFFERENTIAL
DIFF
REF
AMP
INPUT
LOW JITTER
CLOCK
DRIVER
CONTROL LOGIC
AND
CALIBRATION LOGIC
OUTPUT
DRIVERS
OVDD 0.5V TO
5V
OF
D11
D0
CLKOUT
REFLB REFHA
0.1µF
4.7µF
1µF
REFLA REFHB ENC
0.1µF
1µF
ENC
Figure 1. Functional Block Diagram
MSBINV
OGND
1749 F01
1749f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC1749.PDF ] | |
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