PDF LT1678 Data sheet ( Hoja de datos )

Número de pieza	LT1678
Descripción	Dual/Quad Low Noise Rail-to-Rail Precision Op Amps
Fabricantes	Linear Technology
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LTC264ww1w/.DaLtaTSChee2t4U6.co4m2 16-/14-/12-Bit VOUT DACs in 3mm × 3mm DFN FEATURES ■ Tiny 3mm × 3mm 8-Pin DFN Package ■ Maximum 16-Bit INL Error: ±2LSB over Temperature ■ Low 120μA Supply Current ■ Guaranteed Monotonic over Temperature ■ Low 0.5nV•sec Glitch Impulse ■ 2.7V to 5.5V Single Supply Operation ■ Fast 1μs Settling Time to 16 Bits ■ Unbuffered Voltage Output Directly Drives 60k Loads ■ 50MHz SPITM/QSPITM/MICROWIRETM Compatible Serial Interface ■ Power-On Reset Clears DAC Output to Zero Scale (LTC2641) or Midscale (LTC2642) ■ Schmitt-Trigger Inputs for Direct Optocoupler Interface ■ Asynchronous ⎯C⎯L⎯R Pin ■ 8-Lead MSOP and 3mm × 3mm DFN Packages (LTC2641) ■ 10-Lead MSOP and 3mm × 3mm DFN Packages (LTC2642) APPLICATIONS ■ High Resolution Offset and Gain Adjustment ■ Process Control and Industrial Automation ■ Automatic Test Equipment ■ Data Aquisition Systems DESCRIPTION The LTC®2641/LTC2642 are families of 16-, 14- and 12-bit unbuffered voltage output DACs. These DACs operate from a single 2.7V to 5.5V supply and are guaranteed monotonic over temperature. The LTC2641-16/LTC2642-16 provide 16-bit performance (±2LSB INL and ±1LSB DNL) over temperature. Unbuffered DAC outputs result in low supply current of 120μA and a low offset error of ±1LSB. Both the LTC2641 and LTC2642 feature a reference input range of 2V to VDD. VOUT swings from 0V to VREF. For bipolar operation, the LTC2642 includes matched scaling resistors for use with an external precision op amp (such as the LT1678), generating a ±VREF output swing at RFB. The LTC2641/LTC2642 use a simple SPI/MICROWIRE compatible 3-wire serial interface which can be operated at clock rates up to 50MHz and can interface directly with optocouplers for applications requiring isolation. A power-on reset circuit clears the LTC2641’s DAC output to zero scale and the LTC2642’s DAC output to midscale when power is initially applied. A logic low on the ⎯C⎯L⎯R pin asynchronously clears the DAC to zero scale (LTC2641) or midscale (LTC2642). These DACs are all speciﬁed over the commercial and industrial ranges. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 2.7V TO 5.5V Bipolar 16-Bit DAC 0.1μF VREF 1μF 0.1μF 2V TO VDD LTC2642 VDD REF RFB INV 5pF – POWER-ON RESET 16-BIT DAC VOUT 1/2 LT1678 + CS SCLK DIN CLR CONTROL LOGIC 16-BIT DATA LATCH 16-BIT SHIFT REGISTER GND 26412 TA01a BIPOLAR VOUT –VREF TO VREF LTC2642-16 Integral Nonlinearity 1.0 0.8 VDD = 5V VREF = 2.5V 0.6 ±2.5V RANGE 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE INL 25°C INL 90°C INL –45°C 49152 65535 LT1372 • G10 26412f 1 1 page LTC264ww1w/.DaLtaTSChee2t4U6.co4m2 ELECTRICAL CHARACTERISTICS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IIN CIN VH Power Supply Digital Input Current Digital Input Capacitance Hysteresis Voltage VIN = GND to VCC (Note 6) ● ±1 μA ● 3 10 pF 0.15 V VDD Supply Voltage IDD Supply Current, VDD PD Power Dissipation Digital Inputs = 0V or VDD Digital Inputs = 0V or VDD, VDD = 5V Digital Inputs = 0V or VDD, VDD = 3V ● 2.7 5.5 ● 120 200 0.60 0.36 V μA mW mW TIMING CHARACTERISTICS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 fSCLK PARAMETER DIN Valid to SCLK Setup Time DIN Valid to SCLK Hold Time SCLK Pulse Width High SCLK Pulse Width Low ⎯C⎯S Pulse High Width LSB SCLK High to ⎯C⎯S High ⎯C⎯S Low to SCLK High ⎯C⎯S High to SCLK Positive Edge ⎯C⎯L⎯R Pulse Width Low SCLK Frequency VDD High to ⎯C⎯S Low (Power-Up Delay) CONDITIONS 50% Duty Cycle MIN TYP MAX UNITS ● 10 ns ●0 ns ●9 ns ●9 ns ● 10 ns ●8 ns ●8 ns ●8 ns ● 15 ns ● 50 MHz 30 μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the speciﬁed maximum operating junction temperature may impair device reliability. Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale. LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale. Note 4: ROUT tolerance is typically ±20%. Note 5: Reference input resistance is code dependent. Minimum is at 871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar mode. Note 6: Guaranteed by design and not production tested. Note 7: Guaranteed by gain error and offset error testing, not production tested. 26412f 5 5 Page LTC264ww1w/.DaLtaTSChee2t4U6.co4m2 OPERATION The digital-to-analog transfer function at the VOUT pin is: VOUT(IDEAL) = ⎛ ⎝⎜ k⎞ 2N ⎠⎟ VREF where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is between 2.0V and VDD (see Tables 1a, 1b and 1c). The LTC2642 includes matched resistors that are tied to an external ampliﬁer to provide bipolar output swing (Fig- ure 2). The bipolar transfer function at the RFB pin is: VOUT _ BIPOLAR(IDEAL ) = VREF ⎛ ⎝⎜ k 2N–1 – 1⎞⎠⎟ (see Tables 2a, 2b and 2c). Serial Interface The LTC2641/LTC2642 communicates via a standard 3-wire SPI/QSPI/MICROWIRE compatible interface. The chip select input (⎯C⎯S) controls and frames the loading of serial data from the data input (DIN). Following a ⎯C⎯S high-to-low transition, the data on DIN is loaded, MSB ﬁrst, into the shift register on each rising edge of the serial clock input (SCLK). After 16 data bits have been loaded into the serial input register, a low-to-high transition on ⎯C⎯S transfers the data to the 16-bit DAC latch, updating the DAC output (see Figures 1a, 1b, 1c). While ⎯C⎯S remains high, the serial input shift register is disabled. If there are less than 16 low-to-high transitions on SCLK while ⎯C⎯S remains low, the data will be corrupted, and must be reloaded. Also, if there are more than 16 low-to-high transitions on SCLK while ⎯C⎯S remains low, only the last 16 data bits loaded from DIN will be transferred to the DAC latch. For the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB remains in the same (left-justiﬁed) position in the input 16-bit data word. Therefore, two “don’t-care” bits must be loaded after the LSB, to make up the required 16 data bits (Figure 1b). Similarly, for the 12-bit family members (LTC2641-12/LTC2642-12) four “don’t-care” bits must follow the LSB (Figure 1c). CS SCLK DAC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UPDATED DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 26412 F01a DATA (16 BITS) Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16) CS SCLK DAC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UPDATED DIN D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X MSB LSB 26412 F01b DATA (14 BITS + 2 DON’T-CARE BITS) Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14) CS SCLK DAC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UPDATED DIN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X MSB LSB 26412 F01c DATA (12 BITS + 4 DON’T-CARE BITS) Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12) 26412f 11 11 Page

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