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PDF CY8C34 Data sheet ( Hoja de datos )
| Número de pieza | CY8C34 | |
| Descripción | Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY8C34 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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PRELIMINARY
PSoC®3: CY8C34 Family Data Sheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC®3 is a true system level solution providing MCU, memory, analog, and digital
peripheral functions in a single chip. The CY8C34 family offers a modern method of signal acquisition, signal processing, and control
with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to
ultrasonic signals. The CY8C34 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The
CY8C34 family is also a high performance configurable digital system with some part numbers including interfaces such as USB,
multi-master I2C, and CAN. In addition to communication interfaces, the CY8C34 family has an easy to configure logic array, flexible
routing to all I/O pins, and a high performance single cycle 8051 microprocessor core. Designers can easily create system level
designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic design
entry tool. The CY8C34 family provides unparalleled opportunities for analog and digital bill of materials integration while easily
accommodating last minute design changes through simple firmware updates.
Features
Single cycle 8051 CPU core
DC to 48 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, multiple security features
Up to 8 KB Flash ECC or configuration storage
Up to 8 KB SRAM memory
Up to 2 KB EEPROM memory, 1M cycles, 20 years retention
24 channel DMA with multilayer AHB bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low power
Wide operating voltage range: 0.5V to 5.5V
High efficiency boost regulator from 0.5V input to 1.8V-5.0V
output
330 µA at 1 MHz, 1.2 mA at 6 MHz, 5.6 mA at 40 MHz
Low power modes including:
• 200 nA hibernate mode with RAM retention and LVD
www.Dat•aS1hµeeAt4sUle.ceopmmode with real time clock and low voltage reset
Versatile I/O system
28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO[1])
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46x16 segments[1]
1.2V to 5.5V I/O interface voltages, up to 4 domains
Maskable, independent IRQ on any pin or port
Schmitt trigger TTL inputs
All GPIO configurable as open drain high/low, pull up/down,
High-Z, or strong output
Configurable GPIO pin state at power on reset (POR)
25 mA sink on SIO
Digital peripherals
16 to 24 programmable PLD based Universal Digital Blocks
Full CAN 2.0b 16 RX, 8 TX buffers[1]
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[1]
Up to four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8, 16, 24, and 32-bit timers, counters, and PWMs
• SPI, UART, I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic Redundancy Check (CRC)
• Pseudo Random Sequence (PRS) generator
• LIN Bus 2.0
• Quadrature decoder
Analog peripherals (1.71V ≤ Vdda ≤ 5.5V)
1.024V±0.9% internal voltage reference across -40°C to
+85°C (14 ppm/°C)
Configurable Delta-Sigma ADC with 12-bit resolution
• Programmable gain stage: x0.25 to x16
• 12-bit mode, 192 ksps, 70 dB SNR, 1 bit INL/DNL
Two 8-bit, 8 Msps IDACs or 1 Msps VDACs
Four comparators with 75 ns response time
Two uncommitted opamps with 25 mA drive capability
Two configurable multifunction analog blocks. Example con-
figurations are PGA, TIA, Mixer, and Sample and Hold
Programming, debug, and trace
JTAG (4 wire), Serial Wire Debug (SWD) (2 wire), and Single
Wire Viewer (SWV) interfaces
8 address and 1 data breakpoint
4 KB instruction trace buffer
Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
1 to 48 MHz internal ±1% oscillator (over full temperature and
voltage range) with PLL
4 to 33 MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 48 MHz
32.768 kHz watch crystal oscillator
Low power internal oscillator at 1 kHz, 100 kHz
Temperature and packaging
-40°C to +85°C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
package options
Note
1. This feature on select devices only. See Ordering Information on page 92 for details.
Cypress Semiconductor Corporation
Document Number: 001-53304 Rev. *B
• 198 Champion Court
,• San Jose CA 95134-1709
• 408-943-2600
Revised December 03, 2009
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1 page  
PRELIMINARY
PSoC®3: CY8C34 Family Data Sheet
PSoC’s nonvolatile subsystem consists of Flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip Flash. The CPU can reprogram individual
blocks of Flash, enabling boot loaders. The designer can enable
an Error Correcting Code (ECC) for high reliability applications.
A powerful and flexible protection model secures the user's
sensitive information, allowing selective memory block locking
for read and write protection. Up to 2 KB of byte-writable
EEPROM is available on-chip to store application data.
Additionally, selected configuration options such as boot speed
and pin drive mode are stored in nonvolatile memory. This allows
settings to activate immediately after power on reset (POR).
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the Vddio pins. Every GPIO
has analog I/O, LCD drive, CapSense®[4], flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow Voh to be set independently of Vddio when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with Full-Speed USB the USB
physical interface is also provided (USBIO). When not using
USB these pins may also be used for limited digital functionality
and device programming. All the features of the PSoC I/Os are
covered in detail in the “I/O System and Routing” section on
page 29 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability, and factory trimmed for absolute
accuracy. The Internal Main Oscillator (IMO) is the master clock
base for the system with 1% absolute accuracy at 3 MHz. The
IMO can be configured to run from 3 MHz up to 48 MHz. Multiple
wwwc.DloactakShdeeerti4vUat.icvoems can be generated from the main clock
frequency to meet application needs. The device provides a PLL
to generate system clock frequencies up to 48 MHz from the
IMO, external crystal, or external reference clock. It also contains
a separate, very low power Internal Low Speed Oscillator (ILO)
for the sleep and watchdog timers. A 32.768 kHz external watch
crystal is also supported for use in Real Time Clock (RTC) appli-
cations. The clocks, together with programmable clock dividers,
provide the flexibility to integrate most timing requirements.
The CY8C34 family supports a wide supply operating range from
1.71 to 5.5V. This allows operation from regulated supplies such
as 1.8 ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0V ± 10%, or directly
from a wide range of battery types. In addition, it provides an
integrated high efficiency synchronous boost converter that can
power the device from supply voltages as low as 0.5V. This
enables the device to be powered directly from a single battery
or solar cell. In addition, the designer can use the boost converter
to generate other voltages required by the device, such as a 3.3V
supply for LCD glass drive. The boost’s output is available on the
Vboost pin, allowing other devices in the application to be
powered from the PSoC.
PSoC supports a wide range of low power modes. These include
a 200 nA hibernate mode with RAM retention and a 1 µA sleep
mode with real time clock (RTC). In the second mode the
optional 32.768 kHz watch crystal runs continuously and
maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz or 330 µA running at 1 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 25 of this data sheet.
PSoC uses JTAG (4 wire) or Serial Wire Debug (SWD) (2 wire)
interfaces for programming, debug, and test. The 1-wire Single
Wire Viewer (SWV) may also be used for “printf” style debugging.
By combining SWD and SWV, the designer can implement a full
debugging interface with just three pins. Using these standard
interfaces enables the designer to debug or program the PSoC
with a variety of hardware solutions from Cypress or third party
vendors. PSoC supports on-chip break points and 4 KB
instruction and data race memory for debug. Details of the
programming, test, and debugging interfaces are discussed in
the “Programming, Debug Interfaces, Resources” section on
page 57 of this data sheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1
through Figure 2-4. Using the Vddio pins, a single PSoC can
support multiple interface voltage levels, eliminating the need for
off-chip level shifters. Each Vddio may sink up to 100 mA total to
its associated I/O pins and opamps. On the 68 pin and 100 pin
devices each set of Vddio associated pins may sink up to 100
mA. The 48 pin device may sink up to 100 mA total for all Vddio0
plus Vddio2 associated I/O pins and 100 mA total for all Vddio1
plus Vddio3 associated I/O pins.
Document Number: 001-53304 Rev. *B
Page 5 of 99
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PRELIMINARY
PSoC®3: CY8C34 Family Data Sheet
device. All other supply pins must be less than or equal to
Vdda.
Vddd. Supply for all digital peripherals and digital core regulator.
Vddd must be less than or equal to Vdda.
Vssa. Ground for all analog peripherals.
Vssb. Ground connection for boost pump.
Vssd. Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3. Supply for I/O pins. See
pinouts for specific I/O pin to Vddio mapping. Vddio must be less
than or equal to Vdda.
XRES (and configurable XRES). External reset pin. Active low
with internal pullup. In 48-pin SSOP parts, P1[2] is configured as
XRES. In all other parts the pin is configured as a GPIO.
4. CPU
4.1 8051 CPU
The CY8C34 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C34 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 24 MIPS with an average of 2 cycles per
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
The 8051 CPU subsystem includes these features:
Single cycle 8051 CPU
Up to 64 kB of Flash memory, up to 2 kB of EEPROM, and up
to 8 kB of SRAM
Programmable nested vector interrupt controller
Direct Memory Access (DMA) controller
www.DPatearSiphheeert4aUl H.cUomB (PHUB)
External Memory Interface (EMIF)
4.2 Addressing Modes
The following addressing modes are supported by the 8051:
Direct Addressing: The operand is specified by a direct 8-bit
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
Indirect Addressing: The instruction specifies the register which
contains the address of the operand. The registers R0 or R1
are used to specify the 8-bit address, while the Data Pointer
(DPTR) register is used to specify the 16-bit address.
Register Addressing: Certain instructions access one of the
registers (R0-R7) in the specified register bank. These instruc-
tions are more efficient because there is no need for an address
field.
Register Specific Instructions: Some instructions are specific
to certain registers. For example, some instructions always act
on the accumulator. In this case, there is no need to specify the
operand.
Immediate Constants: Some instructions carry the value of the
constants directly instead of an address.
Indexed Addressing: This type of addressing can be used only
for a read of the program memory. This mode uses the Data
Pointer as the base and the accumulator value as an offset to
read a program memory.
Bit Addressing: In this mode, the operand is one of 256 bits.
4.3 Instruction Set
The 8051 instruction set is highly optimized for 8-bit handling and
Boolean operations. The types of instructions supported include:
Arithmetic instructions
Logical instructions
Data transfer instructions
Boolean instructions
Program branching instructions
4.3.1 Instruction Set Summary
4.3.1.1 Arithmetic Instructions
Arithmetic instructions support the direct, indirect, register,
immediate constant, and register specific instructions. Arithmetic
modes are used for addition, subtraction, multiplication, division,
increment, and decrement operations. lists the different arith-
metic instructions.
Document Number: 001-53304 Rev. *B
Page 11 of 99
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet CY8C34.PDF ] | |
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