PDF CY7C4285V Data sheet ( Hoja de datos )

Número de pieza	CY7C4285V
Descripción	32K/64Kx18 Low Voltage Deep Sync FIFOs
Fabricantes	Cypress Semiconductor
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No Preview Available ! 285V CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • 8K x 18 (CY7C4255V) • 16K x 18 (CY7C4265V) • 32K x 18 (CY7C4275V) • 64K x 18 (CY7C4285V) • 0.35 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — ICC = 30 mA — ISB = 4 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • Retransmit function • Output Enable (OE) pin • Independent read and write enable pins • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • 64-pin 10x10 STQFP • Pin-compatible density upgrade to CY7C42X5V-ASC families • Pin-compatible 3.3V solutions for CY7C4255/65/75/85 The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfac- es. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5V Synchronous FIFO family. The CY7C4255/65/75/85V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multipro- cessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are con- trolled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continu- ally written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4255/65/75/85V have an output enable pin (OE). The read and write clocks may be tied togeth- er for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. Clock frequencies up to 67 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devic- es should be tied to VCC. www.DaLtaoShgeiect4BU.lcoomck Diagram D0 – 17 INPUT REGISTER WCLK WEN WRITE CONTROL WRITE POINTER High Density Dual-Port RAM Array 8Kx9 16Kx9 32Kx9 64Kx9 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAE PAF SMODE RS RESET LOGIC FL/RT WXI WXO/HF RXI RXO EXPANSION LOGIC Cypress Semiconductor Corporation • Document #: 38-06012 Rev. A THREE-ST ATE OUTPUT REGISTER READ CONTROL Q0 – 17 OE 3901 North First Street • RCLK REN San Jose 4275V–1 • CA 95134 • 408-943-2600 Revised December 26, 2002 1 page CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V AC Test Loads and Waveforms (-15 -25)[9, 10] 3.3V OUTPUT R1=330Ω CL INCLUDING JIG AND SCOPE R2=510Ω 4275V–4 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns Equivalent to: THÉVENIN EQUIVALENT OUTPUT 200 Ω 2.0V 4287V–5 AC Test Loads and Waveforms (-10) VCC/2 50Ω I/O Z0=50Ω 4275V–6 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns 4275V–7 Switching Characteristics Over the Operating Range 7C4255/65/75/85V 7C4255/65/75/85V 7C4255/65/75/85V -10 -15 -25 Parameter Description Min. Max. Min. Max. Min. Max. Unit tS Clock Cycle Frequency tA Data Access Time www.DatCaSLKheet4U.comClock Cycle Time tCLKH Clock HIGH Time tCLKL Clock LOW Time tDS Data Set-Up Time tDH Data Hold Time tENS Enable Set-Up Time tENH tRS Enable Hold Time Reset Pulse Width[11] tRSR Reset Recovery Time tRSF Reset to Flag and Output Time tPRT Retransmit Pulse Width tRTR tOLZ Retransmit Recovery Time Output Enable to Output in Low Z[12] tOE Output Enable to Output Valid Notes: 9. CL = 30 pF for all AC parameters except for tOHZ. 10. CL = 5 pF for tOHZ. 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. 100 66.7 2 8 2 10 2 10 15 25 4.5 6 10 4.5 6 10 3.5 4 6 001 3.5 4 6 001 10 15 25 8 10 15 10 15 60 60 60 90 90 90 000 3 7 3 10 3 40 MHz 15 ns ns ns ns ns ns ns ns ns ns 25 ns ns ns ns 12 ns Document #: 38-06012 Rev. A Page 5 of 20 5 Page CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms (continued) Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)) tCLKH tCLKL WCLK WEN tENS tENH PAE RCLK REN tSKEW3 [22] Note 21 tPAE synch N + 1 WORDS IN FIFO tENS tENS tENH Note 23 tPAE synch Programmable Almost Full Flag Timing 4275V–16 WCLK WEN tCLKH Note 24 tCLKL tENS tENH www.DataShPeAeFt4[U25.c] om RCLK REN tPAF FULL– M WORDS IN FIFO[26] FULL– (M+1) WORDS IN FIFO [27] tPAF tENS 4275V–17 Notes: 21. PAE offset − n. 22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255V, 16384 − (m + 1) for the CY7C4265V, 32768 − (m + 1) for the CY7C4275V, and 65536 − (m + 1) for the CY7C4285V. 25. PAF is offset = m. 26. 8192 − m words in CY7C4255V, 16384 − m words in CY7C4265V, 32768 − m words in CY7C4275V, and 65536 − m words in CY7C4285V. 27. 8192 − (m + 1) words in CY7C4255V, 16384 − (m + 1) words in CY7C4265V, 32768 − (m + 1) words in CY7C4275V, and 65536 − (m + 1) words in CY7C4285V. Document #: 38-06012 Rev. *A Page 11 of 20 11 Page

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