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Número de pieza | P89LPC917 | |
Descripción | (P89LPC915 - P89LPC917) 8-bit microcontrollers | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de P89LPC917 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
2 kB 3 V Flash with 8-bit A/D converter
Rev. 04 — 17 December 2004
Product data
1. General description
The P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and
16-pin packages, based on a high performance processor architecture that executes
instructions in two to four clocks, six times the rate of standard 80C51 devices. Many
system level functions have been incorporated into the P89LPC915/916/917 in order
to reduce component count, board space, and system cost.
2. Features
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s 2 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
s 256-byte RAM data memory.
s Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC917) may be configured
to toggle a port output upon timer overflow or to become a PWM output.
s 23-bit system timer that can also be used as a Real-Time clock.
s 4-input multiplexed 8-bit A/D converter/single DAC output. Two analog
comparators with selectable reference.
s Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
s SPI communication port (P89LPC916).
s Internal RC oscillator option allows operation without external oscillator
components. The RC oscillator (factory calibrated to ±1 %) option is selectable
and fine tunable.
s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s Up to 14 I/O pins when using internal oscillator and reset options (P89LPC916,
P89LPC917).
3. Additional features
• 14-pin (P89LPC915) and 16-pin (P89LPC916, P89LPC917) TSSOP packages.
• A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
This is six times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
1 page Philips Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
www.DataSheet4U.com
P89LPC916
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
external
clock
input
2 kB
CODE FLASH
256-BYTE
DATA RAM
INTERNAL
BUS
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
CLOCK
ON-CHIP RC
OSCILLATOR
UART
I2C
ADC1/DAC1
SPI
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
ANALOG
COMPARATORS
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
Fig 2. P89LPC916 block diagram.
002aaa823
9397 750 14397
Product data
Rev. 04 — 17 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 72
5 Page Philips Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 4: P89LPC916 pin description…continued
Symbol
Pin
Type Description
P1.0 to P1.5
I/O
(P1.2);
I (P1.5)
Port 1: Port 1 is a 5-bit I/O port with user-configurable outputs. During reset Port 1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the P1.2 input and outputs depends upon the port configuration selected.
Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details. P1.2 is an open drain when used as an output. P1.5 is
input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
10 I/O P1.0 — Port 1 bit 0
O TxD — Serial port transmitter data.
9 I/O P1.1 — Port 1 bit 0
I RxD — Serial port receiver data.
8 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O T0 — Timer/counter 0 external count input, overflow output, or PWM output.
I/O SCL — I2C-bus serial clock input/output.
7 I/O P1.3 — Port 1 bit 2. (Open drain when used as an output.)
I/O INT0 — External interrupt 0 input.
I/O SDA — I2C-bus serial data input/output.
3 I P1.5 — Port 1 bit 5. (Input only.)
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I RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
Also used during a power-on sequence to force In-System Programming mode.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 72
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet P89LPC917.PDF ] |
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