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PDF MAX9249 Data sheet ( Hoja de datos )
| Número de pieza | MAX9249 | |
| Descripción | (MAX9248 - MAX9250) 2.5MHz to 42MHz DC-Balanced LVDS Deserializers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX9249 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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19-3943; Rev 3; 4/09
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
General Description
The MAX9248/MAX9250 digital video serial-to-parallel
converters deserialize a total of 27 bits during data and
control phases. In the data phase, the LVDS serial input is
converted to 18 bits of parallel video data and in the con-
trol phase, the input is converted to 9 bits of parallel con-
trol data. The separate video and control phases take
advantage of video timing to reduce the serial-data rate.
The MAX9248/MAX9250 pair with the MAX9247 serializer
to form a complete digital video transmission system. For
operating frequencies less than 35MHz, the MAX9248/
MAX9250 can also pair with the MAX9217 serializer.
The MAX9248 features spread-spectrum capability,
allowing output data and clock to spread over a speci-
fied frequency range to reduce EMI. The data and
clock outputs are programmable for a spectrum spread
of ±4% or ±2%. The MAX9250 features output enable
input control to allow data busing.
Proprietary data decoding reduces EMI and provides
DC balance. The DC balance allows AC-coupling, pro-
viding isolation between the transmitting and receiving
ends of the interface. The MAX9248/MAX9250 feature a
selectable rising or falling output latch edge.
ESD tolerance is specified for ISO 10605 with ±10kV
Contact Discharge and ±30kV Air-Gap Discharge.
The MAX9248/MAX9250 operate from a +3.3V ±10%
core supply and feature a separate output supply for
interfacing to 1.8V to 3.3V logic-level inputs. These
devices are available in a 48-lead LQFP package and
are specified from -40°C to +85°C or -40°C to +105°C.
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Features
o Programmable ±4% or ±2% Spread-Spectrum
Output for Reduced EMI (MAX9248)
o Proprietary Data Decoding for DC Balance and
Reduced EMI
o Control Data Deserialized During Video Blanking
o Five Control Data Inputs are Single-Bit-Error
Tolerant
o Output Transition Time is Scaled to Operating
Frequency for Reduced EMI
o Staggered Output Switching Reduces EMI
o Output Enable Allows Busing of Outputs
(MAX9250)
o Clock Pulse Stretch on Lock
o Wide ±2% Reference Clock Tolerance
o Synchronizes to MAX9247 Serializer Without
External Control
o ISO 10605 and IEC 61000-4-2 Level 4
ESD Protection
o Separate Output Supply Allows Interface to 1.8V
to 3.3V Logic
o +3.3V Core Power Supply
o Space-Saving LQFP Package
o -40°C to +85°C and -40°C to +105°C Operating
Temperature Ranges
Applications
Navigation System Displays
In-Vehicle Entertainment Systems
Video Cameras
LCD Displays
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9248ECM+
-40°C to +85°C
48 LQFP
MAX9248ECM/V+ -40°C to +85°C
48 LQFP
MAX9248GCM+ -40°C to +105°C
48 LQFP
MAX9248GCM/V+ -40°C to +105°C
48 LQFP
MAX9250ECM+
-40°C to +85°C
48 LQFP
MAX9250ECM/V+ -40°C to +85°C
48 LQFP
MAX9250GCM+ -40°C to +105°C
48 LQFP
MAX9250GCM/V+ -40°C to +105°C
48 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC_ = +3.0V to +3.6V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.1V to 1.2V, input common-mode voltage
VCM = ⏐VID / 2⏐ to VCC - ⏐VID / 2⏐, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 3, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Spread-Spectrum Modulation
Frequency
fSSM Figure 11
fREFCLK /
1024
kHz
Power-Down Delay
SS Change Delay
Output Enable Time
Output Disable Time
tPDD
tΔSSPLL
tOE
tOZ
Figures 7, 8
MAX9248, Figure 17
MAX9250, Figure 8
MAX9250, Figure 9
100
32,800
x tT
10 30
10 30
ns
ns
ns
ns
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ VCC - 0.3V. PWRDWN is ≤ 0.3V, REFCLK is static.
Note 5: CL includes probe and test jig capacitance.
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_______________________________________________________________________________________ 5
5 Page 
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
OUTEN
DE_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
0.8V
tOE
HIGH IMPEDANCE
Figure 9. Output Enable Time
MAX9250
ACTIVE
FREQUENCY
fRxCLKOUT (MAX)
1 / fSSM
fRxCLKIN
TIME
fRxCLKOUT (MIN)
Figure 11. Simplified Modulation Profile
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OUTEN
2.0V
DE_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
tOZ
ACTIVE
Figure 10. Output Disable Time
MAX9250
HIGH IMPEDANCE
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX9249.PDF ] | |
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